| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMParallelDSP.cpp | 121 bool AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1, MemInstList &VecMem);
306 bool ARMParallelDSP::AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1, in AreSequentialLoads() argument
308 if (!Ld0 || !Ld1) in AreSequentialLoads()
313 dbgs() << "Ld1:"; Ld1->dump(); in AreSequentialLoads()
316 if (!Ld0->hasOneUse() || !Ld1->hasOneUse()) { in AreSequentialLoads()
321 return AreSequentialAccesses<LoadInst>(Ld0, Ld1, VecMem, *DL, *SE); in AreSequentialLoads()
364 auto *Ld1 = dyn_cast<LoadInst>(Mul1_LHS[x]); in CreateParallelMACPairs() local
375 if (AreSequentialLoads(Ld0, Ld1, PMul0->VecLd) && in CreateParallelMACPairs()
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| /external/vixl/examples/aarch64/ |
| D | add2-vectors.cc | 59 __ Ld1(v0.V16B(), MemOperand(x0)); in GenerateAdd2Vectors() local
60 __ Ld1(v1.V16B(), MemOperand(x1, 16, PostIndex)); in GenerateAdd2Vectors() local
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| D | neon-matrix-multiply.cc | 73 __ Ld1(v4.V4S(), v5.V4S(), v6.V4S(), v7.V4S(), MemOperand(x1)); in GenerateNEONMatrixMultiply() local
75 __ Ld1(v16.V4S(), v17.V4S(), v18.V4S(), v19.V4S(), MemOperand(x2)); in GenerateNEONMatrixMultiply() local
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| /external/vixl/test/aarch64/ |
| D | test-disasm-neon-aarch64.cc | 349 COMPARE_MACRO(Ld1(v0.M, MemOperand(x15)), "ld1 {v0." S "}, [x15]"); \ in TEST()
350 COMPARE_MACRO(Ld1(v1.M, v2.M, MemOperand(x16)), \ in TEST()
352 COMPARE_MACRO(Ld1(v3.M, v4.M, v5.M, MemOperand(x17)), \ in TEST()
354 COMPARE_MACRO(Ld1(v6.M, v7.M, v8.M, v9.M, MemOperand(x18)), \ in TEST()
356 COMPARE_MACRO(Ld1(v30.M, v31.M, v0.M, v1.M, MemOperand(sp)), \ in TEST()
370 COMPARE_MACRO(Ld1(v0.M, MemOperand(x15, x20, PostIndex)), \ in TEST()
372 COMPARE_MACRO(Ld1(v1.M, v2.M, MemOperand(x16, x21, PostIndex)), \ in TEST()
374 COMPARE_MACRO(Ld1(v3.M, v4.M, v5.M, MemOperand(x17, x22, PostIndex)), \ in TEST()
376 COMPARE_MACRO(Ld1(v6.M, v7.M, v8.M, v9.M, MemOperand(x18, x23, PostIndex)), \ in TEST()
378 COMPARE_MACRO(Ld1(v30.M, v31.M, v0.M, v1.M, MemOperand(sp, x24, PostIndex)), \ in TEST()
[all …]
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| D | test-assembler-neon-aarch64.cc | 312 __ Ld1(v2.V8B(), MemOperand(x17)); in TEST() local
314 __ Ld1(v3.V8B(), v4.V8B(), MemOperand(x17)); in TEST() local
316 __ Ld1(v5.V4H(), v6.V4H(), v7.V4H(), MemOperand(x17)); in TEST() local
318 __ Ld1(v16.V2S(), v17.V2S(), v18.V2S(), v19.V2S(), MemOperand(x17)); in TEST() local
320 __ Ld1(v30.V2S(), v31.V2S(), v0.V2S(), v1.V2S(), MemOperand(x17)); in TEST() local
322 __ Ld1(v20.V1D(), v21.V1D(), v22.V1D(), v23.V1D(), MemOperand(x17)); in TEST() local
368 __ Ld1(v2.V8B(), MemOperand(x17, x23, PostIndex)); in TEST() local
369 __ Ld1(v3.V8B(), v4.V8B(), MemOperand(x18, 16, PostIndex)); in TEST() local
370 __ Ld1(v5.V4H(), v6.V4H(), v7.V4H(), MemOperand(x19, 24, PostIndex)); in TEST() local
371 __ Ld1(v16.V2S(), in TEST() local
[all …]
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| D | test-assembler-aarch64.cc | 11749 __ Ld1(v0.V16B(), MemOperand(x10, x11, PostIndex)); in TEST() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopVectorize/AArch64/ |
| D | reduction-small-size.ll | 127 ; CHECK: [[Ld1:%[a-zA-Z0-9.]+]] = load <8 x i8>
128 ; CHECK: zext <8 x i8> [[Ld1]] to <8 x i16>
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| /external/llvm/test/Transforms/LoopVectorize/AArch64/ |
| D | reduction-small-size.ll | 141 ; CHECK: [[Ld1:%[a-zA-Z0-9.]+]] = load <8 x i8>
142 ; CHECK: zext <8 x i8> [[Ld1]] to <8 x i16>
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| /external/v8/src/codegen/arm64/ |
| D | macro-assembler-arm64.h | 1556 void Ld1(const VRegister& vt, const MemOperand& src) { in Ld1() function
1560 void Ld1(const VRegister& vt, const VRegister& vt2, const MemOperand& src) { in Ld1() function
1564 void Ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, in Ld1() function
1569 void Ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, in Ld1() function
1574 void Ld1(const VRegister& vt, int lane, const MemOperand& src) { in Ld1() function
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.h | 3059 void Ld1(const VRegister& vt, const MemOperand& src) { in Ld1() function
3064 void Ld1(const VRegister& vt, const VRegister& vt2, const MemOperand& src) { in Ld1() function
3069 void Ld1(const VRegister& vt, in Ld1() function
3077 void Ld1(const VRegister& vt, in Ld1() function
3086 void Ld1(const VRegister& vt, int lane, const MemOperand& src) { in Ld1() function
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/autohvx/ |
| D | shuff-combos-128b.ll | 201 ; CHECK: v[[Hd1:[0-9]+]]:[[Ld1:[0-9]+]] = vshuff(v[[Hd0]],v[[Ld0]],[[Rd1]])
202 ; CHECK: v[[Hd2:[0-9]+]]:[[Ld2:[0-9]+]] = vdeal(v[[Hd1]],v[[Ld1]],[[Rd2]])
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| D | shuff-combos-64b.ll | 187 ; CHECK: v[[Hd1:[0-9]+]]:[[Ld1:[0-9]+]] = vdeal(v[[Hd0]],v[[Ld0]],[[Rd1]])
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