| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCELFStreamer.cpp | 109 : sbss[(Log2_64(AccessSize))]; in HexagonMCEmitCommonSymbol()
131 ? ELF::SHN_HEXAGON_SCOMMON + (Log2_64(AccessSize) + 1) in HexagonMCEmitCommonSymbol()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCELFStreamer.cpp | 107 : sbss[(Log2_64(AccessSize))]; in HexagonMCEmitCommonSymbol()
131 ? ELF::SHN_HEXAGON_SCOMMON + (Log2_64(AccessSize) + 1) in HexagonMCEmitCommonSymbol()
|
| /external/llvm/include/llvm/Support/ |
| D | MathExtras.h | 497 inline unsigned Log2_64(uint64_t Value) {
731 int Log2Z = Log2_64(X) + Log2_64(Y);
733 int Log2Max = Log2_64(Max);
|
| /external/swiftshader/third_party/llvm-subzero/include/llvm/Support/ |
| D | MathExtras.h | 519 inline unsigned Log2_64(uint64_t Value) {
789 int Log2Z = Log2_64(X) + Log2_64(Y);
791 int Log2Max = Log2_64(Max);
|
| /external/llvm/lib/Target/X86/ |
| D | X86ShuffleDecodeConstantPool.cpp | 306 unsigned EltMaskSize = Log2_64(NumElements); in DecodeVPERMVMask()
339 unsigned EltMaskSize = Log2_64(NumElements * 2); in DecodeVPERMV3Mask()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblySetP2AlignOperands.cpp | 98 uint64_t P2Align = Log2_64((*MI.memoperands_begin())->getAlignment()); in runOnMachineFunction()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/ |
| D | MathExtras.h | 545 inline unsigned Log2_64(uint64_t Value) {
807 int Log2Z = Log2_64(X) + Log2_64(Y);
809 int Log2Max = Log2_64(Max);
|
| D | Parallel.h | 147 llvm::Log2_64(std::distance(Start, End)) + 1); in parallel_sort()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblySetP2AlignOperands.cpp | 69 uint64_t P2Align = Log2_64((*MI.memoperands_begin())->getAlignment()); in RewriteP2Align()
|
| /external/capstone/ |
| D | MathExtras.h | 281 static inline unsigned Log2_64(uint64_t Value) { in Log2_64() function
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
| D | BPFInstrInfo.cpp | 77 unsigned IterationNum = CopyLen >> Log2_64(Alignment); in expandMEMCPY()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64LegalizerInfo.cpp | 434 MIRBuilder.buildPtrMask(DstPtr, ListTmp, Log2_64(Align)); in legalizeVaArg()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonPatterns.td | 140 return isPowerOf2_64(V) && Log2_64(V) < 32;
145 return isPowerOf2_64(V) && Log2_64(V) >= 32;
150 return isPowerOf2_64(NV) && Log2_64(NV) < 32;
155 return isPowerOf2_64(NV) && Log2_64(NV) >= 32;
185 def Log2_64: SDNodeXForm<imm, [{
187 return CurDAG->getTargetConstant(Log2_64(V), SDLoc(N), MVT::i32);
197 return CurDAG->getTargetConstant(Log2_64(NV), SDLoc(N), MVT::i32);
1602 (S2_setbit_i (LoReg $Rss), (Log2_64 $V)))>;
1604 (Combinew (S2_setbit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))),
1609 (S2_togglebit_i (LoReg $Rss), (Log2_64 $V)))>;
[all …]
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 437 Imm = Log2_64(Imm); in selectBinaryOp()
1747 Imm = Log2_64(Imm); in fastEmit_ri_()
1751 Imm = Log2_64(Imm); in fastEmit_ri_()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 626 Imm = Log2_64(Imm); in selectBinaryOp()
1940 Imm = Log2_64(Imm); in fastEmit_ri_()
1944 Imm = Log2_64(Imm); in fastEmit_ri_()
|
| /external/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 38 return getImm(N, Log2_64((unsigned) N->getZExtValue()));
43 return getImm(N, Log2_64((unsigned) (N->getZExtValue() >> 32)));
|
| D | MipsSEISelLowering.cpp | 812 DAG.getConstant(Log2_64(C), DL, ShiftTy)); in genConstMult()
815 uint64_t Floor = 1LL << Log2_64(C); in genConstMult()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 509 O << Log2_64(MO.getImm()); in PrintAsmOperand()
|
| D | Mips64InstrInfo.td | 33 return getImm(N, Log2_64((unsigned) N->getZExtValue()));
38 return getImm(N, Log2_64((unsigned) (N->getZExtValue() >> 32)));
|
| /external/llvm/lib/MC/MCParser/ |
| D | AsmParser.cpp | 4239 Pow2Alignment = Log2_64(Pow2Alignment); in parseDirectiveComm()
5028 Info.AsmRewrites->emplace_back(AOK_Align, IDLoc, 5, Log2_64(IntValue)); in parseDirectiveMSAlign()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/MC/MCParser/ |
| D | AsmParser.cpp | 4738 Pow2Alignment = Log2_64(Pow2Alignment); in parseDirectiveComm()
5532 Info.AsmRewrites->emplace_back(AOK_Align, IDLoc, 5, Log2_64(IntValue)); in parseDirectiveMSAlign()
|
| /external/clang/lib/AST/ |
| D | Type.cpp | 89 return NumElements.getActiveBits() + llvm::Log2_64(ElementSize); in getNumAddressingBits()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 3914 unsigned Imm = Log2_64(Mask); in optimizeCondBranch()
|
| D | AArch64ISelLowering.cpp | 3678 DAG.getConstant(Log2_64(Mask), dl, MVT::i64), in LowerBR_CC()
3694 DAG.getConstant(Log2_64(Mask), dl, MVT::i64), in LowerBR_CC()
7327 unsigned shift = Log2_64(NumBytes); in isLegalAddressingMode()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 1307 unsigned KnownBits = Log2_64(MaxGPUAlloc / MinGranularity); in LowerFrameIndex()
|