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Searched refs:MAX_BUS_NUM (Results 1 – 11 of 11) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_init.h122 extern u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
156 int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
157 int print_ph(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
158 int read_phase_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
160 int write_leveling_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
161 u32 pup_ph_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], int reg_addr);
Dddr3_training_pbs.c13 u32 nominal_adll[MAX_INTERFACE_NUM * MAX_BUS_NUM];
15 u8 result_mat[MAX_INTERFACE_NUM][MAX_BUS_NUM][BUS_WIDTH_IN_BITS];
16 u8 result_mat_rx_dqs[MAX_INTERFACE_NUM][MAX_BUS_NUM][MAX_CS_NUM];
18 u8 result_all_bit[MAX_BUS_NUM * BUS_WIDTH_IN_BITS * MAX_INTERFACE_NUM];
19 u8 max_pbs_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];
20 u8 min_pbs_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];
21 u8 max_adll_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];
22 u8 min_adll_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];
23 u32 pbsdelay_per_pup[NUM_OF_PBS_MODES][MAX_INTERFACE_NUM][MAX_BUS_NUM][MAX_CS_NUM];
24 u8 adll_shift_lock[MAX_INTERFACE_NUM][MAX_BUS_NUM];
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Dddr3_debug.c90 u32 ctrl_sweepres[ADLL_LENGTH][MAX_INTERFACE_NUM][MAX_BUS_NUM];
91 u32 ctrl_adll[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
92 u32 ctrl_adll1[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
93 u32 ctrl_level_phase[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
565 for (bus_id = 0; bus_id < MAX_BUS_NUM; bus_id++) { in ddr3_tip_print_stability_log()
672 int ddr3_tip_read_adll_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], in ddr3_tip_read_adll_value() argument
706 int ddr3_tip_write_adll_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], in ddr3_tip_write_adll_value() argument
741 int read_phase_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], in read_phase_value() argument
769 int write_leveling_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], in write_leveling_value() argument
770 u32 pup_ph_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], int reg_addr) in write_leveling_value() argument
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Dddr3_training_ip_engine.c16 u32 phy_reg_bk[MAX_INTERFACE_NUM][MAX_BUS_NUM][BUS_WIDTH_IN_BITS];
18 u32 training_res[MAX_INTERFACE_NUM * MAX_BUS_NUM * BUS_WIDTH_IN_BITS *
20 u8 byte_status[MAX_INTERFACE_NUM][MAX_BUS_NUM]; /* holds the bit status in the byte in wrapper func…
43 #if MAX_BUS_NUM == 9
68 #if MAX_BUS_NUM == 9
75 #if MAX_BUS_NUM == 5
100 #if MAX_BUS_NUM == 5
321 [MAX_INTERFACE_NUM * MAX_BUS_NUM * BUS_WIDTH_IN_BITS * search + in ddr3_tip_get_buf_ptr()
322 interface_num * MAX_BUS_NUM * BUS_WIDTH_IN_BITS]; in ddr3_tip_get_buf_ptr()
1112 u8 bit_bit_mask[MAX_BUS_NUM] = { 0 }, bit_bit_mask_active = 0; in ddr3_tip_ip_training_wrapper()
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Dddr3_training_hw_algo.c18 u8 current_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];
19 u8 last_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];
20 u16 current_valid_window[MAX_BUS_NUM][MAX_INTERFACE_NUM];
21 u16 last_valid_window[MAX_BUS_NUM][MAX_INTERFACE_NUM];
22 u8 lim_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];
24 u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
27 static u8 pup_st[MAX_BUS_NUM][MAX_INTERFACE_NUM];
Dddr3_training_leveling.c20 static struct write_supp_result wr_supp_res[MAX_INTERFACE_NUM][MAX_BUS_NUM];
47 u8 rl_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM]; in ddr3_tip_dynamic_read_leveling()
54 for (bus_num = 0; bus_num < MAX_BUS_NUM; bus_num++) in ddr3_tip_dynamic_read_leveling()
403 u32 phyreg3_arr[MAX_INTERFACE_NUM][MAX_BUS_NUM]; in ddr3_tip_dynamic_per_bit_read_leveling()
409 int per_bit_rl_pup_status[MAX_INTERFACE_NUM][MAX_BUS_NUM]; in ddr3_tip_dynamic_per_bit_read_leveling()
410 u32 data2_write[MAX_INTERFACE_NUM][MAX_BUS_NUM]; in ddr3_tip_dynamic_per_bit_read_leveling()
813 u32 res_values[MAX_INTERFACE_NUM * MAX_BUS_NUM] = { 0 }; in ddr3_tip_dynamic_write_leveling()
816 u8 wl_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM]; in ddr3_tip_dynamic_write_leveling()
1675 enum rl_dqs_burst_state rl_state[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; in mv_ddr_rl_dqs_burst()
1687 u32 rl_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; in mv_ddr_rl_dqs_burst()
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Dddr3_training_centralization.c22 u8 bus_end_window[NUM_OF_CENTRAL_TYPES][MAX_INTERFACE_NUM][MAX_BUS_NUM];
23 u8 bus_start_window[NUM_OF_CENTRAL_TYPES][MAX_INTERFACE_NUM][MAX_BUS_NUM];
24 u8 centralization_state[MAX_INTERFACE_NUM][MAX_BUS_NUM];
622 MAX_BUS_NUM]; in ddr3_tip_special_rx()
Dmv_ddr_plat.h11 #define MAX_BUS_NUM 5 macro
Dddr3_training_bist.c491 u32 wr_ctrl_adll[MAX_BUS_NUM] = {0}; in mv_ddr_dm_vw_get()
492 u32 rd_ctrl_adll[MAX_BUS_NUM] = {0}; in mv_ddr_dm_vw_get()
/external/u-boot/include/faraday/
Dftpci100.h51 #define MAX_BUS_NUM 256 macro
/external/u-boot/drivers/pci/
Dpci_ftpci100.c161 for (bus = 0; bus < MAX_BUS_NUM; bus++) in pci_bus_scan()