Searched refs:MC_CGM_ACn_SEL_DDRPLL (Results 1 – 2 of 2) sorted by relevance
63 #define MC_CGM_ACn_SEL_DDRPLL (0x5) macro
236 aux_source_clk_config(MC_CGM0_BASE_ADDR, 8, MC_CGM_ACn_SEL_DDRPLL); in setup_aux_clocks()