Searched refs:MFLR (Results 1 – 18 of 18) sorted by relevance
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativePPC_common.c | 187 #define MFLR (HI(31) | LO(339) | 0x80000) macro
618 FAIL_IF(push_inst(compiler, MFLR | D(0))); in sljit_emit_enter()
1763 return push_inst(compiler, MFLR | D(dst)); in sljit_emit_fast_enter()
1766 FAIL_IF(push_inst(compiler, MFLR | D(TMP_REG2))); in sljit_emit_fast_enter()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 324 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); in getGlobalBaseReg()
328 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); in getGlobalBaseReg()
339 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); in getGlobalBaseReg()
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| D | PPCAsmPrinter.cpp | 805 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::MFLR) in EmitInstruction()
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| D | PPCFrameLowering.cpp | 755 : PPC::MFLR ); in emitPrologue()
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| D | PPCInstrInfo.td | 2332 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
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| D | PPCISelLowering.cpp | 8751 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg); in emitEHSjLjSetJmp()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCAsmPrinter.cpp | 894 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::MFLR) in EmitInstruction()
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| D | PPCFrameLowering.cpp | 765 : PPC::MFLR ); in emitPrologue()
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| D | PPCISelDAGToDAG.cpp | 416 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); in getGlobalBaseReg()
420 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); in getGlobalBaseReg()
431 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); in getGlobalBaseReg()
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| D | PPCInstrInfo.td | 2573 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
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| D | PPCISelLowering.cpp | 10075 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg); in emitEHSjLjSetJmp()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenMCCodeEmitter.inc | 1074 UINT64_C(2080899750), // MFLR
4063 case PPC::MFLR:
6663 0, // MFLR = 1061
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| D | PPCGenAsmWriter.inc | 2679 549087U, // MFLR
4837 0U, // MFLR
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| D | PPCGenInstrInfo.inc | 1076 MFLR = 1061,
3907 …SideEffects), 0x9ULL, ImplicitList12, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1061 = MFLR
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| D | PPCGenDisassemblerTables.inc | 1558 /* 7286 */ MCD::OPC_Decode, 165, 8, 51, // Opcode: MFLR
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| D | PPCGenAsmMatcher.inc | 5830 { 6893 /* mflr */, PPC::MFLR, Convert__RegGPRC1_0, 0, { MCK_RegGPRC }, },
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| /external/capstone/arch/PowerPC/ |
| D | PPCGenDisassemblerTables.inc | 967 /* 3924 */ MCD_OPC_Decode, 165, 5, 35, // Opcode: MFLR
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| D | PPCGenAsmWriter.inc | 697 283677U, // MFLR
1970 0U, // MFLR
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