1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Taken from the linux kernel file of the same name 4 * 5 * (C) Copyright 2012 6 * Graeme Russ, <graeme.russ@gmail.com> 7 */ 8 9 #ifndef _ASM_X86_MSR_INDEX_H 10 #define _ASM_X86_MSR_INDEX_H 11 12 /* CPU model specific register (MSR) numbers */ 13 14 /* x86-64 specific MSRs */ 15 #define MSR_EFER 0xc0000080 /* extended feature register */ 16 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 17 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 18 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 19 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 20 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 21 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 22 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 23 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 24 25 /* EFER bits: */ 26 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 27 #define _EFER_LME 8 /* Long mode enable */ 28 #define _EFER_LMA 10 /* Long mode active (read-only) */ 29 #define _EFER_NX 11 /* No execute enable */ 30 #define _EFER_SVME 12 /* Enable virtualization */ 31 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 32 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 33 34 #define EFER_SCE (1<<_EFER_SCE) 35 #define EFER_LME (1<<_EFER_LME) 36 #define EFER_LMA (1<<_EFER_LMA) 37 #define EFER_NX (1<<_EFER_NX) 38 #define EFER_SVME (1<<_EFER_SVME) 39 #define EFER_LMSLE (1<<_EFER_LMSLE) 40 #define EFER_FFXSR (1<<_EFER_FFXSR) 41 42 /* Intel MSRs. Some also available on other CPUs */ 43 #define MSR_PIC_MSG_CONTROL 0x2e 44 #define PLATFORM_INFO_SET_TDP (1 << 29) 45 46 #define MSR_MTRR_CAP_MSR 0x0fe 47 #define MSR_MTRR_CAP_SMRR (1 << 11) 48 #define MSR_MTRR_CAP_WC (1 << 10) 49 #define MSR_MTRR_CAP_FIX (1 << 8) 50 #define MSR_MTRR_CAP_VCNT 0xff 51 52 #define MSR_IA32_PERFCTR0 0x000000c1 53 #define MSR_IA32_PERFCTR1 0x000000c2 54 #define MSR_FSB_FREQ 0x000000cd 55 #define MSR_NHM_PLATFORM_INFO 0x000000ce 56 57 #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 58 #define NHM_C3_AUTO_DEMOTE (1UL << 25) 59 #define NHM_C1_AUTO_DEMOTE (1UL << 26) 60 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 61 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 62 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 63 64 #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0x000000cd 65 #define MSR_PLATFORM_INFO 0x000000ce 66 #define MSR_PMG_CST_CONFIG_CONTROL 0x000000e2 67 #define SINGLE_PCTL (1 << 11) 68 69 #define MSR_MTRRcap 0x000000fe 70 #define MSR_IA32_BBL_CR_CTL 0x00000119 71 #define MSR_IA32_BBL_CR_CTL3 0x0000011e 72 #define MSR_POWER_MISC 0x00000120 73 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) 74 #define ENABLE_INDP_AUTOCM_MASK (1 << 3) 75 76 #define MSR_EMULATE_PM_TIMER 0x121 77 #define EMULATE_DELAY_OFFSET_VALUE 20 78 #define EMULATE_PM_TMR_EN (1 << 16) 79 #define EMULATE_DELAY_VALUE 0x13 80 81 #define MSR_IA32_SYSENTER_CS 0x00000174 82 #define MSR_IA32_SYSENTER_ESP 0x00000175 83 #define MSR_IA32_SYSENTER_EIP 0x00000176 84 85 #define MSR_IA32_MCG_CAP 0x00000179 86 #define MSR_IA32_MCG_STATUS 0x0000017a 87 #define MSR_IA32_MCG_CTL 0x0000017b 88 89 #define MSR_FLEX_RATIO 0x194 90 #define FLEX_RATIO_LOCK (1 << 20) 91 #define FLEX_RATIO_EN (1 << 16) 92 /* This is burst mode BIT 38 in IA32_MISC_ENABLE MSR at offset 1A0h */ 93 #define BURST_MODE_DISABLE (1 << 6) 94 95 #define MSR_IA32_MISC_ENABLE 0x000001a0 96 97 /* MISC_ENABLE bits: architectural */ 98 #define MISC_ENABLE_FAST_STRING BIT_ULL(0) 99 #define MISC_ENABLE_TCC BIT_ULL(1) 100 #define MISC_DISABLE_TURBO BIT_ULL(6) 101 #define MISC_ENABLE_EMON BIT_ULL(7) 102 #define MISC_ENABLE_BTS_UNAVAIL BIT_ULL(11) 103 #define MISC_ENABLE_PEBS_UNAVAIL BIT_ULL(12) 104 #define MISC_ENABLE_ENHANCED_SPEEDSTEP BIT_ULL(16) 105 #define MISC_ENABLE_MWAIT BIT_ULL(18) 106 #define MISC_ENABLE_LIMIT_CPUID BIT_ULL(22) 107 #define MISC_ENABLE_XTPR_DISABLE BIT_ULL(23) 108 #define MISC_ENABLE_XD_DISABLE BIT_ULL(34) 109 110 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 111 #define MISC_ENABLE_X87_COMPAT BIT_ULL(2) 112 #define MISC_ENABLE_TM1 BIT_ULL(3) 113 #define MISC_ENABLE_SPLIT_LOCK_DISABLE BIT_ULL(4) 114 #define MISC_ENABLE_L3CACHE_DISABLE BIT_ULL(6) 115 #define MISC_ENABLE_SUPPRESS_LOCK BIT_ULL(8) 116 #define MISC_ENABLE_PREFETCH_DISABLE BIT_ULL(9) 117 #define MISC_ENABLE_FERR BIT_ULL(10) 118 #define MISC_ENABLE_FERR_MULTIPLEX BIT_ULL(10) 119 #define MISC_ENABLE_TM2 BIT_ULL(13) 120 #define MISC_ENABLE_ADJ_PREF_DISABLE BIT_ULL(19) 121 #define MISC_ENABLE_SPEEDSTEP_LOCK BIT_ULL(20) 122 #define MISC_ENABLE_L1D_CONTEXT BIT_ULL(24) 123 #define MISC_ENABLE_DCU_PREF_DISABLE BIT_ULL(37) 124 #define MISC_ENABLE_TURBO_DISABLE BIT_ULL(38) 125 #define MISC_ENABLE_IP_PREF_DISABLE BIT_ULL(39) 126 127 #define MSR_TEMPERATURE_TARGET 0x1a2 128 #define MSR_PREFETCH_CTL 0x1a4 129 #define PREFETCH_L1_DISABLE (1 << 0) 130 #define PREFETCH_L2_DISABLE (1 << 2) 131 #define MSR_OFFCORE_RSP_0 0x000001a6 132 #define MSR_OFFCORE_RSP_1 0x000001a7 133 #define MSR_MISC_PWR_MGMT 0x1aa 134 #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) 135 #define MSR_TURBO_RATIO_LIMIT 0x000001ad 136 137 #define MSR_IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 138 #define ENERGY_POLICY_PERFORMANCE 0 139 #define ENERGY_POLICY_NORMAL 6 140 #define ENERGY_POLICY_POWERSAVE 15 141 142 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 143 144 #define PACKAGE_THERM_STATUS_PROCHOT BIT(0) 145 #define PACKAGE_THERM_STATUS_POWER_LIMIT BIT(10) 146 147 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 148 149 #define PACKAGE_THERM_INT_HIGH_ENABLE BIT(0) 150 #define PACKAGE_THERM_INT_LOW_ENABLE BIT(1) 151 #define PACKAGE_THERM_INT_PLN_ENABLE BIT(24) 152 153 #define MSR_LBR_SELECT 0x000001c8 154 #define MSR_LBR_TOS 0x000001c9 155 #define MSR_IA32_PLATFORM_DCA_CAP 0x1f8 156 #define MSR_POWER_CTL 0x000001fc 157 #define MSR_LBR_NHM_FROM 0x00000680 158 #define MSR_LBR_NHM_TO 0x000006c0 159 #define MSR_LBR_CORE_FROM 0x00000040 160 #define MSR_LBR_CORE_TO 0x00000060 161 162 #define MSR_IA32_PEBS_ENABLE 0x000003f1 163 #define MSR_IA32_DS_AREA 0x00000600 164 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 165 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 166 167 #define MSR_MTRRfix64K_00000 0x00000250 168 #define MSR_MTRRfix16K_80000 0x00000258 169 #define MSR_MTRRfix16K_A0000 0x00000259 170 #define MSR_MTRRfix4K_C0000 0x00000268 171 #define MSR_MTRRfix4K_C8000 0x00000269 172 #define MSR_MTRRfix4K_D0000 0x0000026a 173 #define MSR_MTRRfix4K_D8000 0x0000026b 174 #define MSR_MTRRfix4K_E0000 0x0000026c 175 #define MSR_MTRRfix4K_E8000 0x0000026d 176 #define MSR_MTRRfix4K_F0000 0x0000026e 177 #define MSR_MTRRfix4K_F8000 0x0000026f 178 #define MSR_MTRRdefType 0x000002ff 179 180 #define MSR_IA32_CR_PAT 0x00000277 181 182 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 183 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 184 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 185 #define MSR_IA32_LASTINTFROMIP 0x000001dd 186 #define MSR_IA32_LASTINTTOIP 0x000001de 187 188 /* DEBUGCTLMSR bits (others vary by model): */ 189 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 190 /* single-step on branches */ 191 #define DEBUGCTLMSR_BTF (1UL << 1) 192 #define DEBUGCTLMSR_TR (1UL << 6) 193 #define DEBUGCTLMSR_BTS (1UL << 7) 194 #define DEBUGCTLMSR_BTINT (1UL << 8) 195 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 196 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 197 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 198 199 #define MSR_IA32_POWER_CTL 0x000001fc 200 201 #define MSR_IA32_MC0_CTL 0x00000400 202 #define MSR_IA32_MC0_STATUS 0x00000401 203 #define MSR_IA32_MC0_ADDR 0x00000402 204 #define MSR_IA32_MC0_MISC 0x00000403 205 206 /* C-state Residency Counters */ 207 #define MSR_PKG_C3_RESIDENCY 0x000003f8 208 #define MSR_PKG_C6_RESIDENCY 0x000003f9 209 #define MSR_PKG_C7_RESIDENCY 0x000003fa 210 #define MSR_CORE_C3_RESIDENCY 0x000003fc 211 #define MSR_CORE_C6_RESIDENCY 0x000003fd 212 #define MSR_CORE_C7_RESIDENCY 0x000003fe 213 #define MSR_PKG_C2_RESIDENCY 0x0000060d 214 #define MSR_PKG_C8_RESIDENCY 0x00000630 215 #define MSR_PKG_C9_RESIDENCY 0x00000631 216 #define MSR_PKG_C10_RESIDENCY 0x00000632 217 218 /* Run Time Average Power Limiting (RAPL) Interface */ 219 220 #define MSR_PKG_POWER_SKU_UNIT 0x00000606 221 222 #define MSR_C_STATE_LATENCY_CONTROL_0 0x60a 223 #define MSR_C_STATE_LATENCY_CONTROL_1 0x60b 224 #define MSR_C_STATE_LATENCY_CONTROL_2 0x60c 225 #define MSR_C_STATE_LATENCY_CONTROL_3 0x633 226 #define MSR_C_STATE_LATENCY_CONTROL_4 0x634 227 #define MSR_C_STATE_LATENCY_CONTROL_5 0x635 228 #define IRTL_VALID (1 << 15) 229 #define IRTL_1_NS (0 << 10) 230 #define IRTL_32_NS (1 << 10) 231 #define IRTL_1024_NS (2 << 10) 232 #define IRTL_32768_NS (3 << 10) 233 #define IRTL_1048576_NS (4 << 10) 234 #define IRTL_33554432_NS (5 << 10) 235 #define IRTL_RESPONSE_MASK (0x3ff) 236 237 #define MSR_PKG_POWER_LIMIT 0x00000610 238 /* long duration in low dword, short duration in high dword */ 239 #define PKG_POWER_LIMIT_MASK 0x7fff 240 #define PKG_POWER_LIMIT_EN (1 << 15) 241 #define PKG_POWER_LIMIT_CLAMP (1 << 16) 242 #define PKG_POWER_LIMIT_TIME_SHIFT 17 243 #define PKG_POWER_LIMIT_TIME_MASK 0x7f 244 245 #define MSR_PKG_ENERGY_STATUS 0x00000611 246 #define MSR_PKG_PERF_STATUS 0x00000613 247 #define MSR_PKG_POWER_INFO 0x00000614 248 249 #define MSR_DRAM_POWER_LIMIT 0x00000618 250 #define MSR_DRAM_ENERGY_STATUS 0x00000619 251 #define MSR_DRAM_PERF_STATUS 0x0000061b 252 #define MSR_DRAM_POWER_INFO 0x0000061c 253 254 #define MSR_PP0_POWER_LIMIT 0x00000638 255 #define MSR_PP0_ENERGY_STATUS 0x00000639 256 #define MSR_PP0_POLICY 0x0000063a 257 #define MSR_PP0_PERF_STATUS 0x0000063b 258 259 #define MSR_PP1_POWER_LIMIT 0x00000640 260 #define MSR_PP1_ENERGY_STATUS 0x00000641 261 #define MSR_PP1_POLICY 0x00000642 262 #define MSR_CONFIG_TDP_NOMINAL 0x00000648 263 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064c 264 #define MSR_CORE_C1_RES 0x00000660 265 #define MSR_IACORE_RATIOS 0x0000066a 266 #define MSR_IACORE_TURBO_RATIOS 0x0000066c 267 #define MSR_IACORE_VIDS 0x0000066b 268 #define MSR_IACORE_TURBO_VIDS 0x0000066d 269 #define MSR_PKG_TURBO_CFG1 0x00000670 270 #define MSR_CPU_TURBO_WKLD_CFG1 0x00000671 271 #define MSR_CPU_TURBO_WKLD_CFG2 0x00000672 272 #define MSR_CPU_THERM_CFG1 0x00000673 273 #define MSR_CPU_THERM_CFG2 0x00000674 274 #define MSR_CPU_THERM_SENS_CFG 0x00000675 275 276 #define MSR_AMD64_MC0_MASK 0xc0010044 277 278 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 279 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 280 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 281 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 282 283 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 284 285 /* These are consecutive and not in the normal 4er MCE bank block */ 286 #define MSR_IA32_MC0_CTL2 0x00000280 287 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 288 289 #define MSR_P6_PERFCTR0 0x000000c1 290 #define MSR_P6_PERFCTR1 0x000000c2 291 #define MSR_P6_EVNTSEL0 0x00000186 292 #define MSR_P6_EVNTSEL1 0x00000187 293 294 #define MSR_KNC_PERFCTR0 0x00000020 295 #define MSR_KNC_PERFCTR1 0x00000021 296 #define MSR_KNC_EVNTSEL0 0x00000028 297 #define MSR_KNC_EVNTSEL1 0x00000029 298 299 /* Alternative perfctr range with full access. */ 300 #define MSR_IA32_PMC0 0x000004c1 301 302 /* AMD64 MSRs. Not complete. See the architecture manual for a more 303 complete list. */ 304 305 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 306 #define MSR_AMD64_TSC_RATIO 0xc0000104 307 #define MSR_AMD64_NB_CFG 0xc001001f 308 #define MSR_AMD64_PATCH_LOADER 0xc0010020 309 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 310 #define MSR_AMD64_OSVW_STATUS 0xc0010141 311 #define MSR_AMD64_LS_CFG 0xc0011020 312 #define MSR_AMD64_DC_CFG 0xc0011022 313 #define MSR_AMD64_BU_CFG2 0xc001102a 314 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 315 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 316 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 317 #define MSR_AMD64_IBSFETCH_REG_COUNT 3 318 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 319 #define MSR_AMD64_IBSOPCTL 0xc0011033 320 #define MSR_AMD64_IBSOPRIP 0xc0011034 321 #define MSR_AMD64_IBSOPDATA 0xc0011035 322 #define MSR_AMD64_IBSOPDATA2 0xc0011036 323 #define MSR_AMD64_IBSOPDATA3 0xc0011037 324 #define MSR_AMD64_IBSDCLINAD 0xc0011038 325 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 326 #define MSR_AMD64_IBSOP_REG_COUNT 7 327 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 328 #define MSR_AMD64_IBSCTL 0xc001103a 329 #define MSR_AMD64_IBSBRTARGET 0xc001103b 330 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 331 332 /* Fam 16h MSRs */ 333 #define MSR_F16H_L2I_PERF_CTL 0xc0010230 334 #define MSR_F16H_L2I_PERF_CTR 0xc0010231 335 336 /* Fam 15h MSRs */ 337 #define MSR_F15H_PERF_CTL 0xc0010200 338 #define MSR_F15H_PERF_CTR 0xc0010201 339 #define MSR_F15H_NB_PERF_CTL 0xc0010240 340 #define MSR_F15H_NB_PERF_CTR 0xc0010241 341 342 /* Fam 10h MSRs */ 343 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 344 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 345 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 346 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 347 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 348 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 349 #define MSR_FAM10H_NODE_ID 0xc001100c 350 351 /* K8 MSRs */ 352 #define MSR_K8_TOP_MEM1 0xc001001a 353 #define MSR_K8_TOP_MEM2 0xc001001d 354 #define MSR_K8_SYSCFG 0xc0010010 355 #define MSR_K8_INT_PENDING_MSG 0xc0010055 356 /* C1E active bits in int pending message */ 357 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 358 #define MSR_K8_TSEG_ADDR 0xc0010112 359 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 360 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 361 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 362 363 /* K7 MSRs */ 364 #define MSR_K7_EVNTSEL0 0xc0010000 365 #define MSR_K7_PERFCTR0 0xc0010004 366 #define MSR_K7_EVNTSEL1 0xc0010001 367 #define MSR_K7_PERFCTR1 0xc0010005 368 #define MSR_K7_EVNTSEL2 0xc0010002 369 #define MSR_K7_PERFCTR2 0xc0010006 370 #define MSR_K7_EVNTSEL3 0xc0010003 371 #define MSR_K7_PERFCTR3 0xc0010007 372 #define MSR_K7_CLK_CTL 0xc001001b 373 #define MSR_K7_HWCR 0xc0010015 374 #define MSR_K7_FID_VID_CTL 0xc0010041 375 #define MSR_K7_FID_VID_STATUS 0xc0010042 376 377 /* K6 MSRs */ 378 #define MSR_K6_WHCR 0xc0000082 379 #define MSR_K6_UWCCR 0xc0000085 380 #define MSR_K6_EPMR 0xc0000086 381 #define MSR_K6_PSOR 0xc0000087 382 #define MSR_K6_PFIR 0xc0000088 383 384 /* Centaur-Hauls/IDT defined MSRs. */ 385 #define MSR_IDT_FCR1 0x00000107 386 #define MSR_IDT_FCR2 0x00000108 387 #define MSR_IDT_FCR3 0x00000109 388 #define MSR_IDT_FCR4 0x0000010a 389 390 #define MSR_IDT_MCR0 0x00000110 391 #define MSR_IDT_MCR1 0x00000111 392 #define MSR_IDT_MCR2 0x00000112 393 #define MSR_IDT_MCR3 0x00000113 394 #define MSR_IDT_MCR4 0x00000114 395 #define MSR_IDT_MCR5 0x00000115 396 #define MSR_IDT_MCR6 0x00000116 397 #define MSR_IDT_MCR7 0x00000117 398 #define MSR_IDT_MCR_CTRL 0x00000120 399 400 /* VIA Cyrix defined MSRs*/ 401 #define MSR_VIA_FCR 0x00001107 402 #define MSR_VIA_LONGHAUL 0x0000110a 403 #define MSR_VIA_RNG 0x0000110b 404 #define MSR_VIA_BCR2 0x00001147 405 406 /* Transmeta defined MSRs */ 407 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 408 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 409 #define MSR_TMTA_LRTI_READOUT 0x80868018 410 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 411 412 /* Intel defined MSRs. */ 413 #define MSR_IA32_P5_MC_ADDR 0x00000000 414 #define MSR_IA32_P5_MC_TYPE 0x00000001 415 #define MSR_IA32_TSC 0x00000010 416 #define MSR_IA32_PLATFORM_ID 0x00000017 417 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 418 #define MSR_EBC_FREQUENCY_ID 0x0000002c 419 #define MSR_SMI_COUNT 0x00000034 420 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 421 #define MSR_IA32_TSC_ADJUST 0x0000003b 422 423 #define FEATURE_CONTROL_LOCKED (1<<0) 424 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 425 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 426 427 #define MSR_IA32_APICBASE 0x0000001b 428 #define MSR_IA32_APICBASE_BSP (1<<8) 429 #define MSR_IA32_APICBASE_ENABLE (1<<11) 430 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 431 432 #define MSR_IA32_TSCDEADLINE 0x000006e0 433 434 #define MSR_IA32_UCODE_WRITE 0x00000079 435 #define MSR_IA32_UCODE_REV 0x0000008b 436 437 #define MSR_IA32_PERF_STATUS 0x00000198 438 #define MSR_IA32_PERF_CTL 0x00000199 439 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 440 #define MSR_AMD_PERF_STATUS 0xc0010063 441 #define MSR_AMD_PERF_CTL 0xc0010062 442 443 #define MSR_PMG_CST_CONFIG_CTL 0x000000e2 444 #define MSR_PMG_IO_CAPTURE_ADR 0x000000e4 445 #define MSR_IA32_MPERF 0x000000e7 446 #define MSR_IA32_APERF 0x000000e8 447 448 #define MSR_IA32_THERM_CONTROL 0x0000019a 449 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 450 451 #define THERM_INT_HIGH_ENABLE (1 << 0) 452 #define THERM_INT_LOW_ENABLE (1 << 1) 453 #define THERM_INT_PLN_ENABLE (1 << 24) 454 455 #define MSR_IA32_THERM_STATUS 0x0000019c 456 457 #define THERM_STATUS_PROCHOT (1 << 0) 458 #define THERM_STATUS_POWER_LIMIT (1 << 10) 459 460 #define MSR_THERM2_CTL 0x0000019d 461 462 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 463 464 #define MSR_IA32_TSC_DEADLINE 0x000006E0 465 466 /* P4/Xeon+ specific */ 467 #define MSR_IA32_MCG_EAX 0x00000180 468 #define MSR_IA32_MCG_EBX 0x00000181 469 #define MSR_IA32_MCG_ECX 0x00000182 470 #define MSR_IA32_MCG_EDX 0x00000183 471 #define MSR_IA32_MCG_ESI 0x00000184 472 #define MSR_IA32_MCG_EDI 0x00000185 473 #define MSR_IA32_MCG_EBP 0x00000186 474 #define MSR_IA32_MCG_ESP 0x00000187 475 #define MSR_IA32_MCG_EFLAGS 0x00000188 476 #define MSR_IA32_MCG_EIP 0x00000189 477 #define MSR_IA32_MCG_RESERVED 0x0000018a 478 479 /* Pentium IV performance counter MSRs */ 480 #define MSR_P4_BPU_PERFCTR0 0x00000300 481 #define MSR_P4_BPU_PERFCTR1 0x00000301 482 #define MSR_P4_BPU_PERFCTR2 0x00000302 483 #define MSR_P4_BPU_PERFCTR3 0x00000303 484 #define MSR_P4_MS_PERFCTR0 0x00000304 485 #define MSR_P4_MS_PERFCTR1 0x00000305 486 #define MSR_P4_MS_PERFCTR2 0x00000306 487 #define MSR_P4_MS_PERFCTR3 0x00000307 488 #define MSR_P4_FLAME_PERFCTR0 0x00000308 489 #define MSR_P4_FLAME_PERFCTR1 0x00000309 490 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 491 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 492 #define MSR_P4_IQ_PERFCTR0 0x0000030c 493 #define MSR_P4_IQ_PERFCTR1 0x0000030d 494 #define MSR_P4_IQ_PERFCTR2 0x0000030e 495 #define MSR_P4_IQ_PERFCTR3 0x0000030f 496 #define MSR_P4_IQ_PERFCTR4 0x00000310 497 #define MSR_P4_IQ_PERFCTR5 0x00000311 498 #define MSR_P4_BPU_CCCR0 0x00000360 499 #define MSR_P4_BPU_CCCR1 0x00000361 500 #define MSR_P4_BPU_CCCR2 0x00000362 501 #define MSR_P4_BPU_CCCR3 0x00000363 502 #define MSR_P4_MS_CCCR0 0x00000364 503 #define MSR_P4_MS_CCCR1 0x00000365 504 #define MSR_P4_MS_CCCR2 0x00000366 505 #define MSR_P4_MS_CCCR3 0x00000367 506 #define MSR_P4_FLAME_CCCR0 0x00000368 507 #define MSR_P4_FLAME_CCCR1 0x00000369 508 #define MSR_P4_FLAME_CCCR2 0x0000036a 509 #define MSR_P4_FLAME_CCCR3 0x0000036b 510 #define MSR_P4_IQ_CCCR0 0x0000036c 511 #define MSR_P4_IQ_CCCR1 0x0000036d 512 #define MSR_P4_IQ_CCCR2 0x0000036e 513 #define MSR_P4_IQ_CCCR3 0x0000036f 514 #define MSR_P4_IQ_CCCR4 0x00000370 515 #define MSR_P4_IQ_CCCR5 0x00000371 516 #define MSR_P4_ALF_ESCR0 0x000003ca 517 #define MSR_P4_ALF_ESCR1 0x000003cb 518 #define MSR_P4_BPU_ESCR0 0x000003b2 519 #define MSR_P4_BPU_ESCR1 0x000003b3 520 #define MSR_P4_BSU_ESCR0 0x000003a0 521 #define MSR_P4_BSU_ESCR1 0x000003a1 522 #define MSR_P4_CRU_ESCR0 0x000003b8 523 #define MSR_P4_CRU_ESCR1 0x000003b9 524 #define MSR_P4_CRU_ESCR2 0x000003cc 525 #define MSR_P4_CRU_ESCR3 0x000003cd 526 #define MSR_P4_CRU_ESCR4 0x000003e0 527 #define MSR_P4_CRU_ESCR5 0x000003e1 528 #define MSR_P4_DAC_ESCR0 0x000003a8 529 #define MSR_P4_DAC_ESCR1 0x000003a9 530 #define MSR_P4_FIRM_ESCR0 0x000003a4 531 #define MSR_P4_FIRM_ESCR1 0x000003a5 532 #define MSR_P4_FLAME_ESCR0 0x000003a6 533 #define MSR_P4_FLAME_ESCR1 0x000003a7 534 #define MSR_P4_FSB_ESCR0 0x000003a2 535 #define MSR_P4_FSB_ESCR1 0x000003a3 536 #define MSR_P4_IQ_ESCR0 0x000003ba 537 #define MSR_P4_IQ_ESCR1 0x000003bb 538 #define MSR_P4_IS_ESCR0 0x000003b4 539 #define MSR_P4_IS_ESCR1 0x000003b5 540 #define MSR_P4_ITLB_ESCR0 0x000003b6 541 #define MSR_P4_ITLB_ESCR1 0x000003b7 542 #define MSR_P4_IX_ESCR0 0x000003c8 543 #define MSR_P4_IX_ESCR1 0x000003c9 544 #define MSR_P4_MOB_ESCR0 0x000003aa 545 #define MSR_P4_MOB_ESCR1 0x000003ab 546 #define MSR_P4_MS_ESCR0 0x000003c0 547 #define MSR_P4_MS_ESCR1 0x000003c1 548 #define MSR_P4_PMH_ESCR0 0x000003ac 549 #define MSR_P4_PMH_ESCR1 0x000003ad 550 #define MSR_P4_RAT_ESCR0 0x000003bc 551 #define MSR_P4_RAT_ESCR1 0x000003bd 552 #define MSR_P4_SAAT_ESCR0 0x000003ae 553 #define MSR_P4_SAAT_ESCR1 0x000003af 554 #define MSR_P4_SSU_ESCR0 0x000003be 555 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 556 557 #define MSR_P4_TBPU_ESCR0 0x000003c2 558 #define MSR_P4_TBPU_ESCR1 0x000003c3 559 #define MSR_P4_TC_ESCR0 0x000003c4 560 #define MSR_P4_TC_ESCR1 0x000003c5 561 #define MSR_P4_U2L_ESCR0 0x000003b0 562 #define MSR_P4_U2L_ESCR1 0x000003b1 563 564 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 565 566 /* Intel Core-based CPU performance counters */ 567 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 568 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 569 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 570 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 571 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 572 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 573 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 574 575 /* Geode defined MSRs */ 576 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 577 578 /* Intel VT MSRs */ 579 #define MSR_IA32_VMX_BASIC 0x00000480 580 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 581 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 582 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 583 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 584 #define MSR_IA32_VMX_MISC 0x00000485 585 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 586 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 587 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 588 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 589 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 590 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 591 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 592 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 593 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 594 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 595 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 596 #define MSR_IA32_VMX_VMFUNC 0x00000491 597 598 #define MSR_IA32_PQR_ASSOC 0xc8f 599 /* MSR bits 33:32 encode slot number 0-3 */ 600 #define MSR_IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) 601 602 #define MSR_L2_QOS_MASK(reg) (0xd10 + (reg)) 603 604 /* VMX_BASIC bits and bitmasks */ 605 #define VMX_BASIC_VMCS_SIZE_SHIFT 32 606 #define VMX_BASIC_64 0x0001000000000000LLU 607 #define VMX_BASIC_MEM_TYPE_SHIFT 50 608 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 609 #define VMX_BASIC_MEM_TYPE_WB 6LLU 610 #define VMX_BASIC_INOUT 0x0040000000000000LLU 611 612 /* MSR_IA32_VMX_MISC bits */ 613 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 614 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 615 /* AMD-V MSRs */ 616 617 #define MSR_VM_CR 0xc0010114 618 #define MSR_VM_IGNNE 0xc0010115 619 #define MSR_VM_HSAVE_PA 0xc0010117 620 621 #endif /* _ASM_X86_MSR_INDEX_H */ 622