/external/llvm/lib/CodeGen/ |
D | TwoAddressInstructionPass.cpp | 205 unsigned MOReg = MO.getReg(); in sink3AddrInstruction() local 206 if (!MOReg) in sink3AddrInstruction() 208 if (MO.isUse() && MOReg != SavedReg) in sink3AddrInstruction() 274 unsigned MOReg = MO.getReg(); in sink3AddrInstruction() local 275 if (!MOReg) in sink3AddrInstruction() 277 if (DefReg == MOReg) in sink3AddrInstruction() 280 if (MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS))) { in sink3AddrInstruction() 281 if (&OtherMI == KillMI && MOReg == SavedReg) in sink3AddrInstruction() 285 else if (UseRegs.count(MOReg)) in sink3AddrInstruction() 873 unsigned MOReg = MO.getReg(); in rescheduleMIBelowKill() local [all …]
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D | DetectDeadLanes.cpp | 200 unsigned MOReg = MO.getReg(); in addUsedLanesOnOperand() local 201 if (!TargetRegisterInfo::isVirtualRegister(MOReg)) in addUsedLanesOnOperand() 207 UsedLanes &= MRI->getMaxLaneMaskForVReg(MOReg); in addUsedLanesOnOperand() 209 unsigned MORegIdx = TargetRegisterInfo::virtReg2Index(MOReg); in addUsedLanesOnOperand() 383 unsigned MOReg = MO.getReg(); in determineInitialDefinedLanes() local 384 if (!MOReg) in determineInitialDefinedLanes() 388 if (TargetRegisterInfo::isPhysicalRegister(MOReg)) { in determineInitialDefinedLanes() 393 assert(TargetRegisterInfo::isVirtualRegister(MOReg)); in determineInitialDefinedLanes() 394 if (MRI->hasOneDef(MOReg)) { in determineInitialDefinedLanes() 395 const MachineOperand &MODef = *MRI->def_begin(MOReg); in determineInitialDefinedLanes() [all …]
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D | LiveVariables.cpp | 523 unsigned MOReg = MO.getReg(); in runOnInstr() local 525 if (!(TargetRegisterInfo::isPhysicalRegister(MOReg) && in runOnInstr() 526 MRI->isReserved(MOReg))) in runOnInstr() 529 UseRegs.push_back(MOReg); in runOnInstr() 534 if (TargetRegisterInfo::isPhysicalRegister(MOReg) && in runOnInstr() 535 !MRI->isReserved(MOReg)) in runOnInstr() 537 DefRegs.push_back(MOReg); in runOnInstr() 544 unsigned MOReg = UseRegs[i]; in runOnInstr() local 545 if (TargetRegisterInfo::isVirtualRegister(MOReg)) in runOnInstr() 546 HandleVirtRegUse(MOReg, MBB, MI); in runOnInstr() [all …]
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D | MachineInstrBundle.cpp | 312 unsigned MOReg = MO.getReg(); in analyzePhysReg() local 313 if (!MOReg || !TargetRegisterInfo::isPhysicalRegister(MOReg)) in analyzePhysReg() 316 if (!TRI->regsOverlap(MOReg, Reg)) in analyzePhysReg() 319 bool Covered = TRI->isSuperRegisterEq(Reg, MOReg); in analyzePhysReg()
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D | MachineInstr.cpp | 1293 unsigned MOReg = MO.getReg(); in findRegisterUseOperandIdx() local 1294 if (!MOReg) in findRegisterUseOperandIdx() 1296 if (MOReg == Reg || in findRegisterUseOperandIdx() 1298 TargetRegisterInfo::isPhysicalRegister(MOReg) && in findRegisterUseOperandIdx() 1300 TRI->isSubRegister(MOReg, Reg))) in findRegisterUseOperandIdx() 1351 unsigned MOReg = MO.getReg(); in findRegisterDefOperandIdx() local 1352 bool Found = (MOReg == Reg); in findRegisterDefOperandIdx() 1354 TargetRegisterInfo::isPhysicalRegister(MOReg)) { in findRegisterDefOperandIdx() 1356 Found = TRI->regsOverlap(MOReg, Reg); in findRegisterDefOperandIdx() 1358 Found = TRI->isSubRegister(MOReg, Reg); in findRegisterDefOperandIdx() [all …]
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D | TargetInstrInfo.cpp | 1137 const MachineOperand &MOReg = MI.getOperand(OpIdx); in getRegSequenceInputs() local 1142 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(), in getRegSequenceInputs() 1160 const MachineOperand &MOReg = MI.getOperand(1); in getExtractSubregInputs() local 1165 InputReg.Reg = MOReg.getReg(); in getExtractSubregInputs() 1166 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs()
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D | MachineCSE.cpp | 317 unsigned MOReg = MO.getReg(); in PhysRegDefsReach() local 318 if (TargetRegisterInfo::isVirtualRegister(MOReg)) in PhysRegDefsReach() 320 if (PhysRefs.count(MOReg)) in PhysRegDefsReach()
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D | MachineLICM.cpp | 981 unsigned MOReg = MO.getReg(); in HasHighOperandLatency() local 982 if (MOReg != Reg) in HasHighOperandLatency()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
D | TwoAddressInstructionPass.cpp | 234 unsigned MOReg = MO.getReg(); in sink3AddrInstruction() local 235 if (!MOReg) in sink3AddrInstruction() 237 if (MO.isUse() && MOReg != SavedReg) in sink3AddrInstruction() 303 unsigned MOReg = MO.getReg(); in sink3AddrInstruction() local 304 if (!MOReg) in sink3AddrInstruction() 306 if (DefReg == MOReg) in sink3AddrInstruction() 309 if (MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS))) { in sink3AddrInstruction() 310 if (&OtherMI == KillMI && MOReg == SavedReg) in sink3AddrInstruction() 314 else if (UseRegs.count(MOReg)) in sink3AddrInstruction() 915 unsigned MOReg = MO.getReg(); in rescheduleMIBelowKill() local [all …]
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D | DetectDeadLanes.cpp | 198 unsigned MOReg = MO.getReg(); in addUsedLanesOnOperand() local 199 if (!TargetRegisterInfo::isVirtualRegister(MOReg)) in addUsedLanesOnOperand() 205 UsedLanes &= MRI->getMaxLaneMaskForVReg(MOReg); in addUsedLanesOnOperand() 207 unsigned MORegIdx = TargetRegisterInfo::virtReg2Index(MOReg); in addUsedLanesOnOperand() 381 unsigned MOReg = MO.getReg(); in determineInitialDefinedLanes() local 382 if (!MOReg) in determineInitialDefinedLanes() 386 if (TargetRegisterInfo::isPhysicalRegister(MOReg)) { in determineInitialDefinedLanes() 391 assert(TargetRegisterInfo::isVirtualRegister(MOReg)); in determineInitialDefinedLanes() 392 if (MRI->hasOneDef(MOReg)) { in determineInitialDefinedLanes() 393 const MachineOperand &MODef = *MRI->def_begin(MOReg); in determineInitialDefinedLanes() [all …]
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D | LiveVariables.cpp | 523 unsigned MOReg = MO.getReg(); in runOnInstr() local 525 if (!(TargetRegisterInfo::isPhysicalRegister(MOReg) && in runOnInstr() 526 MRI->isReserved(MOReg))) in runOnInstr() 529 UseRegs.push_back(MOReg); in runOnInstr() 534 if (TargetRegisterInfo::isPhysicalRegister(MOReg) && in runOnInstr() 535 !MRI->isReserved(MOReg)) in runOnInstr() 537 DefRegs.push_back(MOReg); in runOnInstr() 544 unsigned MOReg = UseRegs[i]; in runOnInstr() local 545 if (TargetRegisterInfo::isVirtualRegister(MOReg)) in runOnInstr() 546 HandleVirtRegUse(MOReg, MBB, MI); in runOnInstr() [all …]
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D | MachineInstrBundle.cpp | 314 unsigned MOReg = MO.getReg(); in analyzePhysReg() local 315 if (!MOReg || !TargetRegisterInfo::isPhysicalRegister(MOReg)) in analyzePhysReg() 318 if (!TRI->regsOverlap(MOReg, Reg)) in analyzePhysReg() 321 bool Covered = TRI->isSuperRegisterEq(Reg, MOReg); in analyzePhysReg()
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D | MachineInstr.cpp | 768 unsigned MOReg = MO.getReg(); in findRegisterUseOperandIdx() local 769 if (!MOReg) in findRegisterUseOperandIdx() 771 if (MOReg == Reg || (TRI && TargetRegisterInfo::isPhysicalRegister(MOReg) && in findRegisterUseOperandIdx() 773 TRI->isSubRegister(MOReg, Reg))) in findRegisterUseOperandIdx() 824 unsigned MOReg = MO.getReg(); in findRegisterDefOperandIdx() local 825 bool Found = (MOReg == Reg); in findRegisterDefOperandIdx() 827 TargetRegisterInfo::isPhysicalRegister(MOReg)) { in findRegisterDefOperandIdx() 829 Found = TRI->regsOverlap(MOReg, Reg); in findRegisterDefOperandIdx() 831 Found = TRI->isSubRegister(MOReg, Reg); in findRegisterDefOperandIdx() 1652 unsigned MOReg = MO.getReg(); in addRegisterDead() local [all …]
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D | TargetInstrInfo.cpp | 1167 const MachineOperand &MOReg = MI.getOperand(OpIdx); in getRegSequenceInputs() local 1168 if (MOReg.isUndef()) in getRegSequenceInputs() 1174 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(), in getRegSequenceInputs() 1192 const MachineOperand &MOReg = MI.getOperand(1); in getExtractSubregInputs() local 1193 if (MOReg.isUndef()) in getExtractSubregInputs() 1199 InputReg.Reg = MOReg.getReg(); in getExtractSubregInputs() 1200 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs()
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D | MachineCSE.cpp | 340 unsigned MOReg = MO.getReg(); in PhysRegDefsReach() local 341 if (TargetRegisterInfo::isVirtualRegister(MOReg)) in PhysRegDefsReach() 343 if (PhysRefs.count(MOReg)) in PhysRegDefsReach()
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D | MachineLICM.cpp | 1106 unsigned MOReg = MO.getReg(); in HasHighOperandLatency() local 1107 if (MOReg != Reg) in HasHighOperandLatency()
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/external/llvm/lib/Target/SystemZ/ |
D | SystemZElimCompare.cpp | 135 if (unsigned MOReg = MO.getReg()) { in getRegReferences() local 136 if (TRI->regsOverlap(MOReg, Reg)) { in getRegReferences()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
D | SystemZElimCompare.cpp | 153 if (unsigned MOReg = MO.getReg()) { in getRegReferences() local 154 if (TRI->regsOverlap(MOReg, Reg)) { in getRegReferences()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMBaseInstrInfo.cpp | 5003 const MachineOperand *MOReg = &MI.getOperand(1); in getRegSequenceLikeInputs() local 5004 if (!MOReg->isUndef()) in getRegSequenceLikeInputs() 5005 InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(), in getRegSequenceLikeInputs() 5006 MOReg->getSubReg(), ARM::ssub_0)); in getRegSequenceLikeInputs() 5008 MOReg = &MI.getOperand(2); in getRegSequenceLikeInputs() 5009 if (!MOReg->isUndef()) in getRegSequenceLikeInputs() 5010 InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(), in getRegSequenceLikeInputs() 5011 MOReg->getSubReg(), ARM::ssub_1)); in getRegSequenceLikeInputs() 5029 const MachineOperand &MOReg = MI.getOperand(2); in getExtractSubregLikeInputs() local 5030 if (MOReg.isUndef()) in getExtractSubregLikeInputs() [all …]
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/external/llvm/lib/Target/ARM/ |
D | ARMBaseInstrInfo.cpp | 4608 const MachineOperand *MOReg = &MI.getOperand(1); in getRegSequenceLikeInputs() local 4610 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0)); in getRegSequenceLikeInputs() 4612 MOReg = &MI.getOperand(2); in getRegSequenceLikeInputs() 4614 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1)); in getRegSequenceLikeInputs() 4632 const MachineOperand &MOReg = MI.getOperand(2); in getExtractSubregLikeInputs() local 4633 InputReg.Reg = MOReg.getReg(); in getExtractSubregLikeInputs() 4634 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregLikeInputs()
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