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Searched refs:MPIDR_AFFLVL1_VAL (Results 1 – 25 of 33) sorted by relevance

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/external/arm-trusted-firmware/plat/hisilicon/hikey/
Dhikey_pm.c37 cluster = MPIDR_AFFLVL1_VAL(mpidr); in hikey_pwr_domain_on()
39 curr_cluster = MPIDR_AFFLVL1_VAL(read_mpidr()); in hikey_pwr_domain_on()
56 cluster = MPIDR_AFFLVL1_VAL(mpidr); in hikey_pwr_domain_on_finish()
65 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in hikey_pwr_domain_on_finish()
82 cluster = MPIDR_AFFLVL1_VAL(mpidr); in hikey_pwr_domain_off()
90 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in hikey_pwr_domain_off()
121 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in hikey_pwr_domain_suspend()
149 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in hikey_pwr_domain_suspend_finish()
Dhikey_bl31_setup.c85 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in bl31_early_platform_setup2()
/external/arm-trusted-firmware/plat/imx/imx8qm/
Dimx8qm_psci.c77 unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); in imx_pwr_domain_on()
108 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in imx_pwr_domain_on_finish()
117 unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); in imx_pwr_domain_off()
136 unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); in imx_domain_suspend()
154 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in imx_domain_suspend()
167 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in imx_domain_suspend()
212 unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); in imx_domain_suspend_finish()
251 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in imx_domain_suspend_finish()
263 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in imx_domain_suspend_finish()
/external/arm-trusted-firmware/plat/socionext/synquacer/
Dsq_ccn.c36 ccn_enter_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_sq_interconnect_enter_coherency()
44 ccn_exit_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_sq_interconnect_exit_coherency()
/external/arm-trusted-firmware/plat/marvell/common/
Dmarvell_cci.c42 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_marvell_interconnect_enter_coherency()
51 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_marvell_interconnect_exit_coherency()
Dmarvell_topology.c56 cluster_id = MPIDR_AFFLVL1_VAL(mpidr); in marvell_check_mpidr()
/external/arm-trusted-firmware/plat/arm/common/
Darm_cci.c41 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_enter_coherency()
49 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_exit_coherency()
Darm_ccn.c48 ccn_enter_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_enter_coherency()
56 ccn_exit_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_exit_coherency()
/external/arm-trusted-firmware/plat/arm/board/fvp/
Dfvp_topology.c68 cpu_id = MPIDR_AFFLVL1_VAL(mpidr); in plat_core_pos_by_mpidr()
73 clus_id = MPIDR_AFFLVL1_VAL(mpidr); in plat_core_pos_by_mpidr()
/external/arm-trusted-firmware/plat/rockchip/common/aarch64/
Dplatform_common.c78 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_enable()
85 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_disable()
/external/arm-trusted-firmware/plat/socionext/uniphier/
Duniphier_cci.c27 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in __uniphier_cci_enable()
32 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in __uniphier_cci_disable()
/external/arm-trusted-firmware/plat/mediatek/mt8173/aarch64/
Dplatform_common.c83 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_enable()
88 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_disable()
/external/arm-trusted-firmware/plat/renesas/rcar/
Dbl31_plat_setup.c59 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_enable()
64 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_disable()
/external/arm-trusted-firmware/plat/mediatek/mt8183/
Dplat_pm.c306 int cluster = MPIDR_AFFLVL1_VAL(mpidr); in plat_mtk_power_domain_on()
330 int cluster = MPIDR_AFFLVL1_VAL(mpidr); in plat_mtk_power_domain_off()
349 int cluster = MPIDR_AFFLVL1_VAL(mpidr); in plat_mtk_power_domain_on_finish()
365 int cluster = MPIDR_AFFLVL1_VAL(mpidr); in plat_mtk_power_domain_suspend()
405 int cluster = MPIDR_AFFLVL1_VAL(mpidr); in plat_mtk_power_domain_suspend_finish()
/external/arm-trusted-firmware/plat/hisilicon/hikey960/
Dhikey960_pm.c85 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in hikey960_pwr_domain_on_finish()
110 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in hikey960_pwr_domain_off()
215 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in hikey960_pwr_domain_suspend()
Dhikey960_bl31_setup.c90 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in bl31_early_platform_setup2()
/external/arm-trusted-firmware/plat/allwinner/common/
Dsunxi_cpu_ops.c50 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); in sunxi_cpu_off()
86 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); in sunxi_cpu_on()
Dsunxi_topology.c23 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); in plat_core_pos_by_mpidr()
Dsunxi_pm.c30 MPIDR_AFFLVL1_VAL(mpidr) < PLATFORM_CLUSTER_COUNT && \
/external/arm-trusted-firmware/plat/layerscape/board/ls1043/
Dls1043_bl1_setup.c50 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in bl1_early_platform_setup()
Dls1043_bl31_setup.c52 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in bl31_early_platform_setup2()
/external/arm-trusted-firmware/plat/imx/common/
Dimx8_topology.c32 cluster_id = MPIDR_AFFLVL1_VAL(mpidr); in plat_core_pos_by_mpidr()
/external/arm-trusted-firmware/plat/ti/k3/common/
Dk3_topology.c28 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); in plat_core_pos_by_mpidr()
/external/arm-trusted-firmware/plat/mediatek/mt6795/
Dbl31_plat_setup.c116 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_enable()
121 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_disable()
/external/arm-trusted-firmware/plat/rockchip/rk3368/drivers/pmu/
Dpmu.c270 boot_cluster = MPIDR_AFFLVL1_VAL(read_mpidr_el1()); in nonboot_cpus_off()
302 cluster = MPIDR_AFFLVL1_VAL(mpidr); in rockchip_soc_cores_pwr_dm_on()

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