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Searched refs:MPIDR_AFFLVL2 (Results 1 – 25 of 28) sorted by relevance

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/external/arm-trusted-firmware/plat/rockchip/rk3288/include/
Dplatform_def.h38 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
50 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/external/arm-trusted-firmware/plat/rockchip/rk3399/include/
Dplatform_def.h40 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
52 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/external/arm-trusted-firmware/plat/rockchip/rk3328/include/
Dplatform_def.h38 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
50 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/external/arm-trusted-firmware/plat/rockchip/px30/include/
Dplatform_def.h41 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
53 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/external/arm-trusted-firmware/plat/rockchip/rk3368/include/
Dplatform_def.h39 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
53 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/external/arm-trusted-firmware/plat/mediatek/mt6795/
Dplat_pm.c190 assert(afflvl <= MPIDR_AFFLVL2); in plat_do_plat_actions()
348 if (afflvl >= MPIDR_AFFLVL2) { in plat_affinst_suspend()
397 if (afflvl >= MPIDR_AFFLVL2) { in plat_affinst_suspend_finish()
Dplat_topology.c27 return aff_lvl <= MPIDR_AFFLVL2 ? PSCI_AFF_PRESENT : PSCI_AFF_ABSENT; in plat_get_aff_state()
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/
Dplat_psci_handlers.c113 if (lvl == MPIDR_AFFLVL2) in tegra_soc_get_target_pwr_state()
174 } else if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && in tegra_soc_get_target_pwr_state()
192 unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; in tegra_soc_pwr_domain_suspend()
/external/arm-trusted-firmware/plat/hisilicon/hikey/include/
Dplatform_def.h35 #define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2)
/external/arm-trusted-firmware/plat/nvidia/tegra/include/
Dplatform_def.h32 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/external/arm-trusted-firmware/plat/layerscape/board/ls1043/include/
Dls_def.h32 #define LS_PWR_LVL2 MPIDR_AFFLVL2
/external/arm-trusted-firmware/plat/imx/imx8qm/include/
Dplatform_def.h28 #define IMX_PWR_LVL2 MPIDR_AFFLVL2
/external/arm-trusted-firmware/plat/hisilicon/hikey960/include/
Dplatform_def.h32 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/external/arm-trusted-firmware/include/plat/marvell/a3700/common/
Dmarvell_def.h37 #define MARVELL_PWR_LVL2 MPIDR_AFFLVL2
/external/arm-trusted-firmware/include/plat/marvell/a8k/common/
Dmarvell_def.h34 #define MARVELL_PWR_LVL2 MPIDR_AFFLVL2
/external/arm-trusted-firmware/plat/mediatek/mt8173/include/
Dplatform_def.h39 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
/external/arm-trusted-firmware/plat/ti/k3/include/
Dplatform_def.h40 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/external/arm-trusted-firmware/plat/imx/imx8m/imx8mm/include/
Dplatform_def.h22 #define IMX_PWR_LVL2 MPIDR_AFFLVL2
/external/arm-trusted-firmware/plat/imx/imx8m/imx8mq/include/
Dplatform_def.h22 #define IMX_PWR_LVL2 MPIDR_AFFLVL2
/external/arm-trusted-firmware/plat/renesas/rcar/include/
Dplatform_def.h90 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
/external/arm-trusted-firmware/plat/socionext/synquacer/include/
Dplatform_def.h22 #define SQ_PWR_LVL2 MPIDR_AFFLVL2
/external/arm-trusted-firmware/plat/mediatek/mt8183/
Dplat_pm.c368 bool afflvl2 = (pds[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF); in plat_mtk_power_domain_suspend()
407 bool afflvl2 = (pds[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF); in plat_mtk_power_domain_suspend_finish()
/external/arm-trusted-firmware/plat/arm/board/corstone700/include/
Dplatform_def.h106 #define ARM_PWR_LVL2 MPIDR_AFFLVL2
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t194/
Dplat_psci_handlers.c283 if ((lvl == (uint32_t)MPIDR_AFFLVL2) && (states[cpu] == PSTATE_ID_SOC_POWERDN)) { in tegra_soc_get_target_pwr_state()
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/
Dplat_psci_handlers.c254 if ((lvl == (uint32_t)MPIDR_AFFLVL2) && in tegra_soc_get_target_pwr_state()

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