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Searched refs:MRI (Results 1 – 25 of 877) sorted by relevance

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/external/llvm/lib/Target/PowerPC/
DPPCVSXCopy.cpp57 MachineRegisterInfo &MRI) { in IsRegInClass()
59 return RC->hasSubClassEq(MRI.getRegClass(Reg)); in IsRegInClass()
67 bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSReg()
68 return IsRegInClass(Reg, &PPC::VSRCRegClass, MRI); in IsVSReg()
71 bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVRReg()
72 return IsRegInClass(Reg, &PPC::VRRCRegClass, MRI); in IsVRReg()
75 bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) { in IsF8Reg()
76 return IsRegInClass(Reg, &PPC::F8RCRegClass, MRI); in IsF8Reg()
79 bool IsVSFReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSFReg()
80 return IsRegInClass(Reg, &PPC::VSFRCRegClass, MRI); in IsVSFReg()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCVSXCopy.cpp57 MachineRegisterInfo &MRI) { in IsRegInClass()
59 return RC->hasSubClassEq(MRI.getRegClass(Reg)); in IsRegInClass()
67 bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSReg()
68 return IsRegInClass(Reg, &PPC::VSRCRegClass, MRI); in IsVSReg()
71 bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVRReg()
72 return IsRegInClass(Reg, &PPC::VRRCRegClass, MRI); in IsVRReg()
75 bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) { in IsF8Reg()
76 return IsRegInClass(Reg, &PPC::F8RCRegClass, MRI); in IsF8Reg()
79 bool IsVSFReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSFReg()
80 return IsRegInClass(Reg, &PPC::VSFRCRegClass, MRI); in IsVSFReg()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstructionSelector.cpp76 bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
78 bool selectFrameIndexOrGep(MachineInstr &I, MachineRegisterInfo &MRI,
80 bool selectGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI,
82 bool selectConstant(MachineInstr &I, MachineRegisterInfo &MRI,
84 bool selectTruncOrPtrToInt(MachineInstr &I, MachineRegisterInfo &MRI,
86 bool selectZext(MachineInstr &I, MachineRegisterInfo &MRI,
88 bool selectAnyext(MachineInstr &I, MachineRegisterInfo &MRI,
90 bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI,
92 bool selectUadde(MachineInstr &I, MachineRegisterInfo &MRI,
94 bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
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DX86CallLowering.cpp59 MachineRegisterInfo &MRI, in splitToValueTypes() argument
90 ArgInfo{MRI.createGenericVirtualRegister(getLLTForType(*PartTy, DL)), in splitToValueTypes()
103 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in OutgoingValueHandler()
105 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB), in OutgoingValueHandler()
113 unsigned SPReg = MRI.createGenericVirtualRegister(p0); in getStackAddress()
116 unsigned OffsetReg = MRI.createGenericVirtualRegister(SType); in getStackAddress()
119 unsigned AddrReg = MRI.createGenericVirtualRegister(p0); in getStackAddress()
138 MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI); in assignValueToReg()
196 MachineRegisterInfo &MRI = MF.getRegInfo(); in lowerReturn() local
204 if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI, in lowerReturn()
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DX86RegisterBankInfo.cpp110 const MachineInstr &MI, const MachineRegisterInfo &MRI, const bool isFP, in getInstrPartialMappingIdxs() argument
119 OpRegBankIdx[Idx] = getPartialMappingIdx(MRI.getType(MO.getReg()), isFP); in getInstrPartialMappingIdxs()
146 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getSameOperandsMapping() local
149 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getSameOperandsMapping()
151 if (NumOperands != 3 || (Ty != MRI.getType(MI.getOperand(1).getReg())) || in getSameOperandsMapping()
152 (Ty != MRI.getType(MI.getOperand(2).getReg()))) in getSameOperandsMapping()
162 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrMapping() local
199 getInstrPartialMappingIdxs(MI, MRI, /* isFP */ true, OpRegBankIdx); in getInstrMapping()
206 const LLT Ty0 = MRI.getType(Op0.getReg()); in getInstrMapping()
207 const LLT Ty1 = MRI.getType(Op1.getReg()); in getInstrMapping()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp67 MachineRegisterInfo *MRI; member in __anondb39df810111::AArch64AdvSIMDScalar
106 const MachineRegisterInfo *MRI) { in isGPR64() argument
110 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
115 const MachineRegisterInfo *MRI) { in isFPR64() argument
117 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
119 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
129 const MachineRegisterInfo *MRI, in getSrcFromCopy() argument
146 MRI) && in getSrcFromCopy()
147 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
150 MRI) && in getSrcFromCopy()
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DAArch64InstructionSelector.cpp61 MachineRegisterInfo &MRI) const;
63 MachineRegisterInfo &MRI) const;
66 MachineRegisterInfo &MRI) const;
178 const MachineRegisterInfo &MRI, in unsupportedBinOp() argument
180 LLT Ty = MRI.getType(I.getOperand(0).getReg()); in unsupportedBinOp()
203 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp()
326 MachineRegisterInfo &MRI, unsigned SrcReg) { in selectFP16CopyFromGPR32() argument
328 unsigned CopyReg = MRI.createVirtualRegister(&AArch64::FPR32RegClass); in selectFP16CopyFromGPR32()
332 unsigned SubRegCopy = MRI.createVirtualRegister(&AArch64::FPR16RegClass); in selectFP16CopyFromGPR32()
343 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, in selectCopy() argument
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DAArch64CallLowering.cpp55 IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in IncomingArgHandler()
57 : ValueHandler(MIRBuilder, MRI, AssignFn), StackUsed(0) {} in IncomingArgHandler()
64 unsigned AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 64)); in getStackAddress()
104 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in FormalArgHandler()
106 : IncomingArgHandler(MIRBuilder, MRI, AssignFn) {} in FormalArgHandler()
114 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in CallReturnHandler()
116 : IncomingArgHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {} in CallReturnHandler()
126 OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in OutgoingArgHandler()
129 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB), in OutgoingArgHandler()
136 unsigned SPReg = MRI.createGenericVirtualRegister(p0); in getStackAddress()
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/external/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp72 MachineRegisterInfo *MRI; member in __anon9cb25ee90111::AArch64AdvSIMDScalar
113 const MachineRegisterInfo *MRI) { in isGPR64() argument
117 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
122 const MachineRegisterInfo *MRI) { in isFPR64() argument
124 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
126 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
136 const MachineRegisterInfo *MRI, in getSrcFromCopy() argument
153 MRI) && in getSrcFromCopy()
154 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
157 MRI) && in getSrcFromCopy()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DGCNRegPressure.cpp39 const MachineRegisterInfo &MRI) { in printLivesAt() argument
43 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) { in printLivesAt()
53 dbgs() << " " << printReg(Reg, MRI.getTargetRegisterInfo()) in printLivesAt()
86 const MachineRegisterInfo &MRI) { in getRegKind() argument
88 const auto RC = MRI.getRegClass(Reg); in getRegKind()
89 auto STI = static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo()); in getRegKind()
98 const MachineRegisterInfo &MRI) { in inc() argument
108 const auto MaxMask = MRI.getMaxLaneMaskForVReg(Reg); in inc()
110 switch (auto Kind = getRegKind(Reg, MRI)) { in inc()
127 Value[Kind] += Sign * MRI.getPressureSets(Reg).getWeight(); in inc()
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DAMDGPURegisterBankInfo.cpp57 const MachineRegisterInfo &MRI = MF->getRegInfo(); in isConstant() local
58 const MachineInstr *Def = MRI.getVRegDef(MO.getReg()); in isConstant()
103 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrAlternativeMappings() local
109 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrAlternativeMappings()
138 unsigned Size = getSizeInBits(MI.getOperand(2).getReg(), MRI, *TRI); in getInstrAlternativeMappings()
194 const MachineRegisterInfo &MRI = MF.getRegInfo(); in isSALUMapping() local
197 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI); in isSALUMapping()
207 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getDefaultMappingSOP() local
211 unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI); in getDefaultMappingSOP()
221 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getDefaultMappingVOP() local
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DSIFixSGPRCopies.cpp148 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in hasVGPROperands() local
154 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVGPROperands()
163 const MachineRegisterInfo &MRI) { in getCopyRegClasses() argument
169 MRI.getRegClass(SrcReg) : in getCopyRegClasses()
177 MRI.getRegClass(DstReg) : in getCopyRegClasses()
198 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in tryChangeVGPRtoSGPRinCopy() local
206 for (const auto &MO : MRI.reg_nodbg_operands(DstReg)) { in tryChangeVGPRtoSGPRinCopy()
216 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
236 MachineRegisterInfo &MRI) { in foldVGPRCopyIntoRegSequence() argument
240 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()
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DAMDGPUInstructionSelector.cpp67 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectCOPY() local
74 TRI.getConstrainedRegClassForOperand(MO, MRI); in selectCOPY()
77 RBI.constrainGenericRegister(MO.getReg(), *RC, MRI); in selectCOPY()
89 MachineRegisterInfo &MRI = MF->getRegInfo(); in getSubOperand64() local
90 unsigned DstReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); in getSubOperand64()
125 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectG_ADD() local
126 unsigned Size = RBI.getSizeInBits(I.getOperand(0).getReg(), MRI, TRI); in selectG_ADD()
127 unsigned DstLo = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_ADD()
128 unsigned DstHi = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_ADD()
158 RBI.constrainGenericRegister(MO.getReg(), AMDGPU::SReg_64RegClass, MRI); in selectG_ADD()
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/
DMIPatternMatch.h25 bool mi_match(Reg R, MachineRegisterInfo &MRI, Pattern &&P) { in mi_match() argument
26 return P.match(MRI, R); in mi_match()
35 bool match(const MachineRegisterInfo &MRI, unsigned Reg) { in match()
36 return MRI.hasOneUse(Reg) && SubPat.match(MRI, Reg); in match()
48 bool match(const MachineRegisterInfo &MRI, unsigned Reg) { in match()
49 if (auto MaybeCst = getConstantVRegVal(Reg, MRI)) { in match()
65 bool match(const MachineRegisterInfo &MRI, unsigned Reg) { return true; } in match()
66 bool match(const MachineRegisterInfo &MRI, MachineOperand *MO) { in match()
76 bool match(MachineRegisterInfo &MRI, MatchSrc &&src) { in match()
88 bool match(MachineRegisterInfo &MRI, MatchSrc &&src) {
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DLegalizationArtifactCombiner.h27 MachineRegisterInfo &MRI; variable
31 LegalizationArtifactCombiner(MachineIRBuilder &B, MachineRegisterInfo &MRI, in LegalizationArtifactCombiner() argument
33 : Builder(B), MRI(MRI), LI(LI) {} in LegalizationArtifactCombiner()
40 MI.getOperand(1).getReg(), MRI)) { in tryCombineAnyExt()
59 MI.getOperand(1).getReg(), MRI)) { in tryCombineZExt()
61 LLT DstTy = MRI.getType(DstReg); in tryCombineZExt()
68 LLT ZExtSrcTy = MRI.getType(ZExtSrc); in tryCombineZExt()
87 MI.getOperand(1).getReg(), MRI)) { in tryCombineSExt()
89 LLT DstTy = MRI.getType(DstReg); in tryCombineSExt()
97 LLT SExtSrcTy = MRI.getType(SExtSrc); in tryCombineSExt()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp48 MachineRegisterInfo &MRI) const;
60 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
66 bool validOpRegPair(MachineRegisterInfo &MRI, unsigned LHS, unsigned RHS,
70 bool validReg(MachineRegisterInfo &MRI, unsigned Reg, unsigned ExpectedSize,
121 MachineRegisterInfo &MRI, in guessRegClass() argument
124 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
127 const unsigned Size = MRI.getType(Reg).getSizeInBits(); in guessRegClass()
147 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, in selectCopy() argument
153 const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI); in selectCopy()
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DARMRegisterBankInfo.cpp215 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrMapping() local
250 LLT LargeTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
260 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
273 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
280 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
294 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
295 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
303 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
304 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
313 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
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/external/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp116 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in hasVGPROperands() local
122 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVGPROperands()
131 const MachineRegisterInfo &MRI) { in getCopyRegClasses() argument
137 MRI.getRegClass(SrcReg) : in getCopyRegClasses()
145 MRI.getRegClass(DstReg) : in getCopyRegClasses()
179 MachineRegisterInfo &MRI) { in foldVGPRCopyIntoRegSequence() argument
183 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()
186 if (!MRI.hasOneUse(DstReg)) in foldVGPRCopyIntoRegSequence()
189 MachineInstr &CopyUse = *MRI.use_instr_begin(DstReg); in foldVGPRCopyIntoRegSequence()
194 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); in foldVGPRCopyIntoRegSequence()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyPeephole.cpp63 MachineRegisterInfo &MRI) { in MaybeRewriteToDrop() argument
67 unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in MaybeRewriteToDrop()
78 MachineRegisterInfo &MRI, in MaybeRewriteToFallthrough() argument
100 unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg)); in MaybeRewriteToFallthrough()
119 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnMachineFunction() local
150 if (MRI.getRegClass(NewReg) != MRI.getRegClass(OldReg)) in runOnMachineFunction()
153 Changed |= MaybeRewriteToDrop(OldReg, NewReg, MO, MFI, MRI); in runOnMachineFunction()
162 MI, MBB, MF, MFI, MRI, TII, WebAssembly::FALLTHROUGH_RETURN_I32, in runOnMachineFunction()
167 MI, MBB, MF, MFI, MRI, TII, WebAssembly::FALLTHROUGH_RETURN_I64, in runOnMachineFunction()
172 MI, MBB, MF, MFI, MRI, TII, WebAssembly::FALLTHROUGH_RETURN_F32, in runOnMachineFunction()
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DWebAssemblyRegColoring.cpp66 static float computeWeight(const MachineRegisterInfo *MRI, in computeWeight() argument
70 for (MachineOperand &MO : MRI->reg_nodbg_operands(VReg)) in computeWeight()
89 MachineRegisterInfo *MRI = &MF.getRegInfo(); in runOnMachineFunction() local
96 unsigned NumVRegs = MRI->getNumVirtRegs(); in runOnMachineFunction()
106 if (MRI->use_empty(VReg)) in runOnMachineFunction()
111 LI->weight = computeWeight(MRI, MBFI, VReg); in runOnMachineFunction()
122 [MRI](LiveInterval *LHS, LiveInterval *RHS) { in runOnMachineFunction()
123 if (MRI->isLiveIn(LHS->reg) != MRI->isLiveIn(RHS->reg)) in runOnMachineFunction()
124 return MRI->isLiveIn(LHS->reg); in runOnMachineFunction()
142 const TargetRegisterClass *RC = MRI->getRegClass(Old); in runOnMachineFunction()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
DUtils.cpp31 unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI, in constrainRegToClass() argument
36 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) { in constrainRegToClass()
37 unsigned NewReg = MRI.createVirtualRegister(&RegClass); in constrainRegToClass()
49 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass() argument
67 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); in constrainOperandRegClass()
85 return constrainRegToClass(MRI, TII, RBI, InsertPt, Reg, *RegClass); in constrainOperandRegClass()
96 MachineRegisterInfo &MRI = MF.getRegInfo(); in constrainSelectedInstRegOperands() local
121 MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), in constrainSelectedInstRegOperands()
136 const MachineRegisterInfo &MRI) { in isTriviallyDead() argument
150 !MRI.use_nodbg_empty(Reg)) in isTriviallyDead()
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/external/swiftshader/third_party/llvm-7.0/llvm/unittests/CodeGen/GlobalISel/
DPatternMatchTest.cpp135 MachineRegisterInfo &MRI = MF->getRegInfo(); in TEST() local
139 bool match = mi_match(MIBCst->getOperand(0).getReg(), MRI, m_ICst(Cst)); in TEST()
156 MachineRegisterInfo &MRI = MF->getRegInfo(); in TEST() local
162 mi_match(MIBAdd->getOperand(0).getReg(), MRI, m_GAdd(m_Reg(), m_Reg())); in TEST()
165 match = mi_match(MIBAdd->getOperand(0).getReg(), MRI, in TEST()
175 match = mi_match(MIBMul->getOperand(0).getReg(), MRI, in TEST()
182 match = mi_match(MIBMul->getOperand(0).getReg(), MRI, in TEST()
194 match = mi_match(MIBMul2->getOperand(0).getReg(), MRI, in TEST()
202 match = mi_match(MIBSub->getOperand(0).getReg(), MRI, in TEST()
209 match = mi_match(MIBFMul->getOperand(0).getReg(), MRI, in TEST()
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/external/llvm/lib/Target/WebAssembly/
DWebAssemblyRegColoring.cpp63 static float computeWeight(const MachineRegisterInfo *MRI, in computeWeight() argument
67 for (MachineOperand &MO : MRI->reg_nodbg_operands(VReg)) in computeWeight()
86 MachineRegisterInfo *MRI = &MF.getRegInfo(); in runOnMachineFunction() local
93 unsigned NumVRegs = MRI->getNumVirtRegs(); in runOnMachineFunction()
103 if (MRI->use_empty(VReg)) in runOnMachineFunction()
108 LI->weight = computeWeight(MRI, MBFI, VReg); in runOnMachineFunction()
119 [MRI](LiveInterval *LHS, LiveInterval *RHS) { in runOnMachineFunction()
120 if (MRI->isLiveIn(LHS->reg) != MRI->isLiveIn(RHS->reg)) in runOnMachineFunction()
121 return MRI->isLiveIn(LHS->reg); in runOnMachineFunction()
139 const TargetRegisterClass *RC = MRI->getRegClass(Old); in runOnMachineFunction()
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DWebAssemblyPeephole.cpp60 MachineRegisterInfo &MRI) { in MaybeRewriteToDrop() argument
64 unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in MaybeRewriteToDrop()
75 MachineRegisterInfo &MRI, in MaybeRewriteToFallthrough() argument
91 unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg)); in MaybeRewriteToFallthrough()
109 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnMachineFunction() local
138 Changed |= MaybeRewriteToDrop(OldReg, NewReg, MO, MFI, MRI); in runOnMachineFunction()
159 if (MRI.getRegClass(NewReg) != MRI.getRegClass(OldReg)) in runOnMachineFunction()
162 Changed |= MaybeRewriteToDrop(OldReg, NewReg, MO, MFI, MRI); in runOnMachineFunction()
171 MI, MBB, MF, MFI, MRI, TII, WebAssembly::FALLTHROUGH_RETURN_I32, in runOnMachineFunction()
176 MI, MBB, MF, MFI, MRI, TII, WebAssembly::FALLTHROUGH_RETURN_I64, in runOnMachineFunction()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMIRCanonicalizerPass.cpp241 MachineRegisterInfo *MRI = &MBB->getParent()->getRegInfo(); in rescheduleCanonically() local
242 for (auto &UO : MRI->use_nodbg_operands(MO.getReg())) { in rescheduleCanonically()
323 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); in propagateLocalCopies() local
345 if (MRI.getRegClass(Dst) != MRI.getRegClass(Src)) in propagateLocalCopies()
348 for (auto UI = MRI.use_begin(Dst); UI != MRI.use_end(); ++UI) { in propagateLocalCopies()
368 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); in populateCandidates() local
379 for (auto UI = MRI.use_begin(Dst); UI != MRI.use_end(); ++UI) { in populateCandidates()
402 const MachineRegisterInfo &MRI = MF.getRegInfo(); in doCandidateWalk() local
421 MRI.def_begin(Reg)->dump(); in doCandidateWalk()
436 for (auto RI = MRI.def_begin(Reg), RE = MRI.def_end(); RI != RE; ++RI) { in doCandidateWalk()
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