| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | thumbv8m.s | 200 MSR PSP_NS, r2 label
204 MSR CONTROL_NS, r4 label
212 MSR MSPLIM,r8 label
214 MSR PSPLIM,r9 label
219 MSR PSPLIM_NS, r11 label
224 MSR FAULTMASK_NS, r14 label
231 MSR 146, r8 label
|
| D | thumbv7m.s | 22 @ MSR
|
| D | thumbv7em.s | 10 @ MSR
|
| D | thumb2-mclass.s | 38 @ MSR
|
| /external/llvm/test/MC/ARM/ |
| D | thumbv8m.s | 200 MSR PSP_NS, r2 label
204 MSR CONTROL_NS, r4 label
212 MSR MSPLIM,r8 label
214 MSR PSPLIM,r9 label
220 MSR PSPLIM_NS, r11 label
229 MSR FAULTMASK_NS, r14 label
|
| D | thumbv7m.s | 22 @ MSR
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| D | thumbv7em.s | 10 @ MSR
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| D | thumb2-mclass.s | 38 @ MSR
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | flags-multiuse.ll | 25 ; Currently, the comparison is emitted again. An MSR/MRS pair would also be
|
| /external/google-breakpad/src/third_party/libdisasm/ |
| D | TODO | 22 * sysenter, sysexit as CALL types -- preceded by MSR writes
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | flags-multiuse.ll | 28 ; Currently, the comparison is emitted again. An MSR/MRS pair would also be
|
| /external/u-boot/doc/ |
| D | README.mpc85xx | 7 - MSR[DE] must be set
11 To maximize the time during which this requirement is met, U-Boot sets MSR[DE]
|
| /external/llvm/test/CodeGen/SystemZ/ |
| D | int-mul-02.ll | 7 ; Check MSR.
133 ; Check that multiplications of spilled values can use MS rather than MSR.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/ |
| D | int-mul-02.ll | 7 ; Check MSR.
133 ; Check that multiplications of spilled values can use MS rather than MSR.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | invalid-armv7.txt | 246 # A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate)
506 # Undefined encodings for MSR/MRS (banked register)
|
| D | thumb-MSR-MClass.txt | 39 # MSR
|
| /external/crosvm/devices/src/ |
| D | serial.rs | 24 const MSR: u8 = 6; constant
390 MSR => { in read()
|
| /external/llvm/test/CodeGen/ARM/ |
| D | copy-cpsr.ll | 26 ; In Thumb mode v7M and v7AR have different MRS/MSR instructions that happen
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb-MSR-MClass.txt | 39 # MSR
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | copy-cpsr.ll | 26 ; In Thumb mode v7M and v7AR have different MRS/MSR instructions that happen
|
| /external/OpenCSD/decoder/tests/snapshots/juno_r1_1/ds-5-dumps/ |
| D | Trace_Report_0x15_cpu_5_2015Sep17_105126.txt | 409 EL1N:0xFFFFFFC00008572C D51BD040 MSR TPIDR_EL0,x0
410 EL1N:0xFFFFFFC000085730 D51BD061 MSR TPIDRRO_EL0,x1
432 EL1N:0xFFFFFFC000085730 D51BD061 MSR TPIDRRO_EL0,x1
569 EL1N:0xFFFFFFC000083C1C D50348FF MSR DAIFClr,#8
571 EL1N:0xFFFFFFC000083C24 D50342FF MSR DAIFClr,#2
1009 EL1N:0xFFFFFFC000083C30 D50342DF MSR DAIFSet,#2
1016 EL1N:0xFFFFFFC000083C4C D5184035 MSR ELR_EL1,x21
1017 EL1N:0xFFFFFFC000083C50 D5184016 MSR SPSR_EL1,x22
1172 EL1N:0xFFFFFFC0000841EC D50342DF MSR DAIFSet,#2
1185 EL1N:0xFFFFFFC000084230 D5184035 MSR ELR_EL1,x21
[all …]
|
| D | Trace_Report_0x13_cpu_3_2015Sep17_104147.txt | 6 EL1N:0xFFFFFFC000096A08 D5182000 MSR TTBR0_EL1,x0
43 EL1N:0xFFFFFFC000083D9C D50348FF MSR DAIFClr,#8
101 EL1N:0xFFFFFFC0000A2E2C D50342DF MSR DAIFSet,#2
193 EL1N:0xFFFFFFC0000A2E64 D50342DF MSR DAIFSet,#2
227 EL1N:0xFFFFFFC0000A2E64 D50342DF MSR DAIFSet,#2
411 EL1N:0xFFFFFFC0000ABE08 D50342FF MSR DAIFClr,#2
499 EL1N:0xFFFFFFC000083DC4 D5184035 MSR ELR_EL1,x21
500 EL1N:0xFFFFFFC000083DC8 D5184016 MSR SPSR_EL1,x22
520 EL1N:0xFFFFFFC000085180 D50341FF MSR DAIFClr,#1
|
| /external/mesa3d/src/gallium/drivers/swr/rasterizer/common/ |
| D | isa.hpp | 70 bool MSR(void) { return CPU_Rep.f_1_EDX_[5]; } in MSR() function in InstructionSet
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrHTM.td | 90 // value of the MSR Transaction State (TS) bits that exist before the
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrHTM.td | 90 // value of the MSR Transaction State (TS) bits that exist before the
|