| /external/u-boot/arch/mips/cpu/ |
| D | start.S | 39 MTC0 zero, CP0_WATCHLO,\sel
194 MTC0 zero, CP0_WATCHLO
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| /external/u-boot/arch/mips/lib/ |
| D | genex.S | 149 MTC0 v1, CP0_EPC
196 MTC0 k1, CP0_DESAVE
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| /external/u-boot/arch/mips/include/asm/ |
| D | asm.h | 407 #define MTC0 mtc0 macro
411 #define MTC0 dmtc0 macro
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 658 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012) in emitInterruptPrologueStub()
741 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP014) in emitInterruptEpilogueStub()
749 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012) in emitInterruptEpilogueStub()
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| D | MipsInstrInfo.td | 2052 def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd, II_MTC0>, MFC3OP_FM<0x10, 4>,
2257 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 683 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012) in emitInterruptPrologueStub()
765 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP014) in emitInterruptEpilogueStub()
773 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012) in emitInterruptEpilogueStub()
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| D | MipsScheduleP5600.td | 85 MFC0, MTC0)>;
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| D | MipsInstrInfo.td | 2421 def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd, II_MTC0>,
2721 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>,
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 684 {DBGFIELD("MTC0") 1, false, false, 19, 2, 7, 1, 0, 0}, // #409
1704 {DBGFIELD("MTC0") 1, false, false, 38, 3, 1, 1, 0, 0}, // #409
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| D | MipsGenAsmWriter.inc | 3166 1376288823U, // MTC0
5797 0U, // MTC0
6865 // MTTC0, DMTC0, DMTC2, DMTGC0, MTC0, MTC0_MMR6, MTC2, MTGC0, MTGC0_MM, M...
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| D | MipsGenMCCodeEmitter.inc | 1951 UINT64_C(1082130432), // MTC0
6486 case Mips::MTC0:
9677 Feature_HasStdEnc | Feature_NotInMicroMips | 0, // MTC0 = 1938
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| D | MipsGenInstrInfo.inc | 1953 MTC0 = 1938,
3066 MTC0 = 409,
5998 …modeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1938 = MTC0
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| D | MipsGenAsmMatcher.inc | 6770 …{ 6652 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc…
6772 …{ 6652 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature…
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| D | MipsGenDisassemblerTables.inc | 3142 /* 1741 */ MCD::OPC_Decode, 146, 15, 191, 1, // Opcode: MTC0
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 1171 1107312657U, // MTC0
2885 0U, // MTC0
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| D | MipsGenDisassemblerTables.inc | 748 /* 1363 */ MCD_OPC_Decode, 130, 9, 58, // Opcode: MTC0
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 5197 case Mips::MTC0: in checkTargetMatchPredicate()
|