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Searched refs:MUBUF (Results 1 – 25 of 42) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dmubuf.ll6 ;;; MUBUF LOAD TESTS
9 ; MUBUF load with an immediate byte offset that fits into 12-bits
20 ; MUBUF load with the largest possible immediate offset
31 ; MUBUF load with an immediate byte offset that doesn't fit into 12-bits
43 ; MUBUF load with a 12-bit immediate offset and a register offset
90 ;;; MUBUF STORE TESTS
93 ; MUBUF store with an immediate byte offset that fits into 12-bits
103 ; MUBUF store with the largest possible immediate offset
114 ; MUBUF store with an immediate byte offset that doesn't fit into 12-bits
125 ; MUBUF store with a 12-bit immediate offset and a register offset
Dschedule-global-loads.ll23 ; an MUBUF load which does not have a vaddr operand.
Dlocal-stack-slot-offset.ll6 ; MUBUF instructions, so a new base register is needed. This used to not
Dmubuf-offset-private.ll136 ; MUBUF used for stack access has bounds checking enabled before gfx9,
/external/llvm/test/CodeGen/AMDGPU/
Dmubuf.ll6 ;;; MUBUF LOAD TESTS
9 ; MUBUF load with an immediate byte offset that fits into 12-bits
20 ; MUBUF load with the largest possible immediate offset
31 ; MUBUF load with an immediate byte offset that doesn't fit into 12-bits
43 ; MUBUF load with a 12-bit immediate offset and a register offset
88 ;;; MUBUF STORE TESTS
91 ; MUBUF store with an immediate byte offset that fits into 12-bits
101 ; MUBUF store with the largest possible immediate offset
112 ; MUBUF store with an immediate byte offset that doesn't fit into 12-bits
123 ; MUBUF store with a 12-bit immediate offset and a register offset
Dschedule-global-loads.ll24 ; an MUBUF load which does not have a vaddr operand.
Dconcat_vectors.ll5 ; 0x80f000 is the high 32 bits of the resource descriptor used by MUBUF
/external/mesa3d/src/amd/compiler/
Daco_opcodes.py43 MUBUF = 10 variable in Format
88 elif self == Format.MUBUF:
1249 MUBUF = { variable
1331 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in MUBUF:
1332 opcode(name, gfx7, gfx9, gfx10, Format.MUBUF, is_atomic = "atomic" in name)
Daco_opt_value_numbering.cpp105 case Format::MUBUF: in operator ()()
270 case Format::MUBUF: { in operator ()()
Daco_ir.cpp142 case Format::MUBUF: in get_sync_info()
Daco_validate.cpp215 … ((instr->format == Format::MUBUF || instr->format == Format::MTBUF) && i == 1); in validate_ir()
429 case Format::MUBUF: { in validate_ir()
Daco_ir.h83 MUBUF = 10, enumerator
938 format == Format::MUBUF || in isVMEM()
Daco_print_ir.cpp364 case Format::MUBUF: { in print_instr_format_specific()
Daco_insert_NOPs.cpp494 bool consider_buf = (instr->format == Format::MUBUF || instr->format == Format::MTBUF) && in handle_instruction_gfx6()
/external/llvm/docs/
DAMDGPUUsage.rst55 MUBUF Instructions
57 All non-atomic MUBUF instructions are supported.
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td928 // MUBUF Instructions
2159 (!cast<MUBUF>(opcode # _OFFSET) $rsrc, $soffset, (as_i16imm $offset),
2167 (!cast<MUBUF>(opcode # _IDXEN) $vindex, $rsrc, $soffset, (as_i16imm $offset),
2175 (!cast<MUBUF>(opcode # _OFFEN) $voffset, $rsrc, $soffset, (as_i16imm $offset),
2183 (!cast<MUBUF>(opcode # _BOTHEN)
2203 (!cast<MUBUF>(opcode # _OFFSET) $vdata, $rsrc, $soffset, (as_i16imm $offset),
2211 (!cast<MUBUF>(opcode # _IDXEN) $vdata, $vindex, $rsrc, $soffset,
2220 (!cast<MUBUF>(opcode # _OFFEN) $vdata, $voffset, $rsrc, $soffset,
2229 (!cast<MUBUF>(opcode # _BOTHEN)
2252 (!cast<MUBUF>(opcode # _RTN_OFFSET) $vdata_in, $rsrc, $soffset,
[all …]
DSIInstrFormats.td38 field bits<1> MUBUF = 0;
74 let TSFlags{16} = MUBUF;
686 class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> :
691 let MUBUF = 1;
DSIDefines.h35 MUBUF = 1 << 16, enumerator
DSIInstrInfo.h280 return MI.getDesc().TSFlags & SIInstrFlags::MUBUF; in isMUBUF()
284 return get(Opcode).TSFlags & SIInstrFlags::MUBUF; in isMUBUF()
DCIInstructions.td100 // MUBUF Instructions
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td49 field bit MUBUF = 0;
144 let TSFlags{16} = MUBUF;
DSIDefines.h46 MUBUF = 1 << 16, enumerator
DSIInstrInfo.h405 return MI.getDesc().TSFlags & SIInstrFlags::MUBUF; in isMUBUF()
409 return get(Opcode).TSFlags & SIInstrFlags::MUBUF; in isMUBUF()
DAMDGPU.td369 // to missing ADDR64 variants of MUBUF instructions.
370 // FIXME: moveToVALU should be able to handle converting addr64 MUBUF
DBUFInstructions.td290 // MUBUF classes
308 let MUBUF = 1;
695 // MUBUF Instructions
1030 // MUBUF Patterns

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