/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t194/ |
D | plat_memctrl.c | 148 mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE), 149 mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), 150 mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE), 151 mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE), 152 mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 153 mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE), 154 mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE), 155 mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE), 156 mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE), 157 mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE), [all …]
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/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/ |
D | plat_memctrl.c | 97 mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, DISABLE), 98 mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, ENABLE), 99 mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, ENABLE), 100 mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE), 101 mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE), 102 mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), 103 mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE), 104 mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE), 106 mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE), 107 mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), [all …]
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/external/arm-trusted-firmware/services/spd/tspd/ |
D | tspd_main.c | 67 ns_cpu_context = cm_get_context(NON_SECURE); in tspd_handle_sp_preemption() 80 cm_el1_sysregs_context_restore(NON_SECURE); in tspd_handle_sp_preemption() 81 cm_set_next_eret_context(NON_SECURE); in tspd_handle_sp_preemption() 105 assert(get_interrupt_src_ss(flags) == NON_SECURE); in tspd_sel1_interrupt_handler() 108 assert(handle == cm_get_context(NON_SECURE)); in tspd_sel1_interrupt_handler() 111 cm_el1_sysregs_context_save(NON_SECURE); in tspd_sel1_interrupt_handler() 345 ns_cpu_context = cm_get_context(NON_SECURE); in tspd_smc_handler() 353 cm_el1_sysregs_context_restore(NON_SECURE); in tspd_smc_handler() 354 cm_set_next_eret_context(NON_SECURE); in tspd_smc_handler() 388 set_interrupt_rm_flag(flags, NON_SECURE); in tspd_smc_handler() [all …]
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/external/arm-trusted-firmware/bl32/sp_min/ |
D | sp_min_main.c | 49 assert(security_state == NON_SECURE); 55 assert(security_state == NON_SECURE); in smc_set_next_ctx() 71 assert(security_state == NON_SECURE); in cm_get_context() 81 assert(security_state == NON_SECURE); in cm_set_context() 94 assert(security_state == NON_SECURE); in cm_get_context_by_index() 105 assert(security_state == NON_SECURE); in cm_set_context_by_index() 128 cpu_context_t *ctx = cm_get_context(NON_SECURE); in sp_min_prepare_next_image_entry() 134 assert(NON_SECURE == GET_SECURITY_STATE(next_image_info->h.attr)); in sp_min_prepare_next_image_entry() 139 smc_set_next_ctx(NON_SECURE); in sp_min_prepare_next_image_entry() 142 copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)), in sp_min_prepare_next_image_entry() [all …]
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/external/arm-trusted-firmware/services/spd/opteed/ |
D | opteed_main.c | 62 assert(get_interrupt_src_ss(flags) == NON_SECURE); in opteed_sel1_interrupt_handler() 65 assert(handle == cm_get_context(NON_SECURE)); in opteed_sel1_interrupt_handler() 68 cm_el1_sysregs_context_save(NON_SECURE); in opteed_sel1_interrupt_handler() 216 assert(handle == cm_get_context(NON_SECURE)); in opteed_smc_handler() 218 cm_el1_sysregs_context_save(NON_SECURE); in opteed_smc_handler() 301 set_interrupt_rm_flag(flags, NON_SECURE); in opteed_smc_handler() 367 ns_cpu_context = cm_get_context(NON_SECURE); in opteed_smc_handler() 371 cm_el1_sysregs_context_restore(NON_SECURE); in opteed_smc_handler() 372 cm_set_next_eret_context(NON_SECURE); in opteed_smc_handler() 382 ns_cpu_context = cm_get_context(NON_SECURE); in opteed_smc_handler() [all …]
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/external/arm-trusted-firmware/services/spd/trusty/ |
D | trusty.c | 92 ctx_smc = cm_get_context(NON_SECURE); in trusty_context_switch() 139 ret = trusty_context_switch(NON_SECURE, SMC_FC_FIQ_ENTER, 0, 0, 0); in trusty_fiq_handler() 156 cm_set_elr_spsr_el3(NON_SECURE, ctx->fiq_handler_pc, (uint32_t)ctx->fiq_handler_cpsr); in trusty_fiq_handler() 197 ret = trusty_context_switch(NON_SECURE, SMC_FC_FIQ_EXIT, 0, 0, 0); in trusty_fiq_exit() 215 cm_set_elr_spsr_el3(NON_SECURE, ctx->fiq_pc, (uint32_t)ctx->fiq_cpsr); in trusty_fiq_exit() 278 ret = trusty_context_switch(NON_SECURE, smc_fid, x1, in trusty_smc_handler() 302 fpregs_context_save(get_fpregs_ctx(cm_get_context(NON_SECURE))); in trusty_init() 303 cm_el1_sysregs_context_save(NON_SECURE); in trusty_init() 327 cm_el1_sysregs_context_restore(NON_SECURE); in trusty_init() 328 fpregs_context_restore(get_fpregs_ctx(cm_get_context(NON_SECURE))); in trusty_init() [all …]
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/external/arm-trusted-firmware/services/spd/tlkd/ |
D | tlkd_main.c | 177 ns_cpu_context = cm_get_context(NON_SECURE); in tlkd_smc_handler() 185 cm_el1_sysregs_context_restore(NON_SECURE); in tlkd_smc_handler() 186 cm_set_next_eret_context(NON_SECURE); in tlkd_smc_handler() 225 assert(handle == cm_get_context(NON_SECURE)); in tlkd_smc_handler() 240 cm_el1_sysregs_context_save(NON_SECURE); in tlkd_smc_handler() 321 ns_cpu_context = cm_get_context(NON_SECURE); in tlkd_smc_handler() 334 cm_el1_sysregs_context_restore(NON_SECURE); in tlkd_smc_handler() 335 cm_set_next_eret_context(NON_SECURE); in tlkd_smc_handler()
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D | tlkd_common.c | 31 cm_el1_sysregs_context_restore(NON_SECURE); in tlkd_va_translate() 34 write_scr(cm_get_scr_el3(NON_SECURE)); in tlkd_va_translate()
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/external/arm-trusted-firmware/bl1/ |
D | bl1_fwu.c | 244 if (GET_SECURITY_STATE(image_desc->ep_info.h.attr) == NON_SECURE) { in bl1_fwu_image_copy() 514 (GET_SECURITY_STATE(image_desc->ep_info.h.attr) == NON_SECURE) || in bl1_fwu_image_execute() 525 cm_el1_sysregs_context_save(NON_SECURE); in bl1_fwu_image_execute() 556 if (caller_sec_state == NON_SECURE) { in bl1_fwu_image_resume() 575 resume_sec_state = NON_SECURE; in bl1_fwu_image_resume() 618 if (GET_SECURITY_STATE(flags) == NON_SECURE) { in bl1_fwu_sec_image_done() 649 cm_el1_sysregs_context_restore(NON_SECURE); in bl1_fwu_sec_image_done() 652 cm_set_next_eret_context(NON_SECURE); in bl1_fwu_sec_image_done() 654 *handle = cm_get_context(NON_SECURE); in bl1_fwu_sec_image_done() 657 cm_set_next_context(cm_get_context(NON_SECURE)); in bl1_fwu_sec_image_done() [all …]
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/external/arm-trusted-firmware/plat/nvidia/tegra/common/ |
D | tegra_fiq_glue.c | 45 cpu_context_t *ctx = cm_get_context(NON_SECURE); in tegra_fiq_interrupt_handler() 72 cm_el1_sysregs_context_save(NON_SECURE); in tegra_fiq_interrupt_handler() 85 cm_set_elr_el3(NON_SECURE, ns_fiq_handler_addr); in tegra_fiq_interrupt_handler() 130 set_interrupt_rm_flag((flags), (NON_SECURE)); in tegra_fiq_handler_setup() 156 cpu_context_t *ctx = cm_get_context(NON_SECURE); in tegra_fiq_get_intr_context()
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/external/arm-trusted-firmware/plat/mediatek/mt6795/ |
D | bl31_plat_setup.c | 159 next_image_info = (type == NON_SECURE) ? in bl31_plat_get_next_image_ep_info() 230 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2() 366 SET_SECURITY_STATE(next_image_info->h.attr, NON_SECURE); in bl31_plat_get_next_kernel64_ep_info() 412 SET_SECURITY_STATE(next_image_info->h.attr, NON_SECURE); in bl31_plat_get_next_kernel32_ep_info() 431 image_type = NON_SECURE; in bl31_prepare_kernel_entry()
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/external/arm-trusted-firmware/services/std_svc/spm_mm/ |
D | spm_mm_main.c | 251 cm_el1_sysregs_context_save(NON_SECURE); in mm_communicate() 257 cm_el1_sysregs_context_restore(NON_SECURE); in mm_communicate() 258 cm_set_next_eret_context(NON_SECURE); in mm_communicate() 331 assert(handle == cm_get_context(NON_SECURE)); in spm_mm_smc_handler()
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/external/arm-trusted-firmware/bl31/ |
D | bl31_context_mgmt.c | 23 assert(security_state <= NON_SECURE); in cm_get_context() 34 assert(security_state <= NON_SECURE); in cm_set_context()
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/external/arm-trusted-firmware/include/common/ |
D | ep_info.h | 20 #define NON_SECURE EP_NON_SECURE macro 21 #define sec_state_is_valid(s) (((s) == SECURE) || ((s) == NON_SECURE))
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/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/ |
D | plat_sip_calls.c | 59 cm_set_elr_spsr_el3(NON_SECURE, x1, in plat_sip_handler() 63 cm_write_scr_el3_bit(NON_SECURE, SCR_RW_BITPOS, !x2); in plat_sip_handler()
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/external/arm-trusted-firmware/plat/xilinx/zynqmp/ |
D | bl31_zynqmp_setup.c | 35 if (type == NON_SECURE) in bl31_plat_get_next_image_ep_info() 91 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2() 178 set_interrupt_rm_flag(flags, NON_SECURE); in bl31_plat_runtime_setup()
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/external/arm-trusted-firmware/services/std_svc/sdei/ |
D | sdei_intr_mgmt.c | 225 cm_el1_sysregs_context_restore(NON_SECURE); in restore_and_resume_ns_context() 226 cm_set_next_eret_context(NON_SECURE); in restore_and_resume_ns_context() 228 ns_ctx = cm_get_context(NON_SECURE); in restore_and_resume_ns_context() 265 cm_set_elr_spsr_el3(NON_SECURE, (uintptr_t) se->ep, in setup_ns_dispatch() 648 ctx = cm_get_context(NON_SECURE); in sdei_event_complete() 656 cm_set_elr_spsr_el3(NON_SECURE, pc, SPSR_64(client_el, in sdei_event_complete()
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/external/arm-trusted-firmware/bl1/tbbr/ |
D | tbbr_img_desc.c | 27 VERSION_1, entry_point_info_t, NON_SECURE | EXECUTABLE), 58 VERSION_1, entry_point_info_t, NON_SECURE),
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/external/arm-trusted-firmware/plat/arm/common/aarch64/ |
D | arm_bl2_mem_params_desc.c | 89 VERSION_2, entry_point_info_t, NON_SECURE | NON_EXECUTABLE), 172 VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), 194 VERSION_2, entry_point_info_t, NON_SECURE | NON_EXECUTABLE),
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D | execution_state_switch.c | 158 | NON_SECURE | EP_ST_DISABLE)); in arm_execution_state_switch() 166 cm_prepare_el3_exit(NON_SECURE); in arm_execution_state_switch()
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/external/arm-trusted-firmware/lib/psci/ |
D | psci_setup.c | 72 NON_SECURE); in psci_init_pwr_domain_node() 301 assert(GET_SECURITY_STATE(next_image_info->h.attr) == NON_SECURE); in psci_prepare_next_non_secure_ctx() 303 cm_prepare_el3_exit(NON_SECURE); in psci_prepare_next_non_secure_ctx()
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/external/arm-trusted-firmware/plat/arm/common/aarch32/ |
D | arm_bl2_mem_params_desc.c | 61 VERSION_2, entry_point_info_t, NON_SECURE | NON_EXECUTABLE), 71 VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
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/external/arm-trusted-firmware/plat/xilinx/versal/ |
D | bl31_versal_setup.c | 37 if (type == NON_SECURE) in bl31_plat_get_next_image_ep_info() 94 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2()
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/external/arm-trusted-firmware/plat/marvell/common/ |
D | marvell_bl31_setup.c | 49 next_image_info = (type == NON_SECURE) in bl31_plat_get_next_image_ep_info() 99 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in marvell_bl31_early_platform_setup()
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/external/arm-trusted-firmware/plat/allwinner/common/ |
D | sunxi_bl31_setup.c | 102 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2() 185 if (type == NON_SECURE) in bl31_plat_get_next_image_ep_info()
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