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Searched refs:NUM_BYTE_LANES (Results 1 – 5 of 5) sorted by relevance

/external/u-boot/arch/x86/include/asm/arch-quark/
Dmrc.h18 #define NUM_BYTE_LANES 4 /* number of byte lanes per channel */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
/external/u-boot/arch/x86/cpu/quark/
Dsmc.c307 bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; in ddrphy_init()
938 bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; in ddrphy_init()
974 bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; in ddrphy_init()
1010 bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; in ddrphy_init()
1062 bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; in ddrphy_init()
1358 for (bl = 0; bl < NUM_BYTE_LANES; bl++) { in restore_timings()
1386 for (bl = 0; bl < NUM_BYTE_LANES; bl++) { in default_timings()
1411 uint32_t final_delay[NUM_CHANNELS][NUM_BYTE_LANES]; in rcvn_cal()
1422 uint32_t delay[NUM_BYTE_LANES]; in rcvn_cal()
1458 for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) in rcvn_cal()
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Dmrc_util.c1043 for (bl_grp = 0; bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { in sample_dqs()
1093 bool direction[NUM_BYTE_LANES]; /* direction indicator */ in find_rising_edge()
1111 for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { in find_rising_edge()
1136 for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { in find_rising_edge()
1201 for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { in find_rising_edge()
1264 for (j = 0; j < MAX_BYTE_LANES; j += NUM_BYTE_LANES) in byte_lane_mask()
1265 ret_val |= (1 << ((j / NUM_BYTE_LANES) * NUM_BYTE_LANES)); in byte_lane_mask()
1359 for (bl = 0; bl < NUM_BYTE_LANES; bl++) { in clear_pointers()
1411 for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { in print_timings_internal()
Dsmc.h161 #define DDRIODQ_CH_OFFSET ((NUM_BYTE_LANES / 2) * DDRIODQ_BL_OFFSET)
/external/u-boot/arch/arm/mach-exynos/
Ddmc_init_ddr3.c20 #define NUM_BYTE_LANES 4 macro
352 int start, int end, int results[NUM_BYTE_LANES]) in test_shifts() argument
357 for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) { in test_shifts()
409 int left[NUM_BYTE_LANES]; in software_find_read_offset()
410 int right[NUM_BYTE_LANES]; in software_find_read_offset()
429 for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) { in software_find_read_offset()