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Searched refs:NumLanes (Results 1 – 22 of 22) sorted by relevance

/external/llvm/lib/Target/X86/Utils/
DX86ShuffleDecode.cpp97 unsigned NumLanes = VectorSizeInBits / 128; in DecodeMOVDDUPMask() local
98 unsigned NumLaneElts = NumElts / NumLanes; in DecodeMOVDDUPMask()
110 unsigned NumLanes = VectorSizeInBits / 128; in DecodePSLLDQMask() local
111 unsigned NumLaneElts = NumElts / NumLanes; in DecodePSLLDQMask()
124 unsigned NumLanes = VectorSizeInBits / 128; in DecodePSRLDQMask() local
125 unsigned NumLaneElts = NumElts / NumLanes; in DecodePSRLDQMask()
141 unsigned NumLanes = VT.getSizeInBits() / 128; in DecodePALIGNRMask() local
142 unsigned NumLaneElts = NumElts / NumLanes; in DecodePALIGNRMask()
160 unsigned NumLanes = VT.getSizeInBits() / 128; in DecodePSHUFMask() local
161 if (NumLanes == 0) NumLanes = 1; // Handle MMX in DecodePSHUFMask()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/Utils/
DX86ShuffleDecode.cpp151 unsigned NumLanes = Size / 128; in DecodePSHUFMask() local
152 if (NumLanes == 0) NumLanes = 1; // Handle MMX in DecodePSHUFMask()
153 unsigned NumLaneElts = NumElts / NumLanes; in DecodePSHUFMask()
228 unsigned NumLanes = (NumElts * ScalarBits) / 128; in DecodeUNPCKHMask() local
229 if (NumLanes == 0) NumLanes = 1; // Handle MMX in DecodeUNPCKHMask()
230 unsigned NumLaneElts = NumElts / NumLanes; in DecodeUNPCKHMask()
247 unsigned NumLanes = (NumElts * ScalarBits) / 128; in DecodeUNPCKLMask() local
248 if (NumLanes == 0 ) NumLanes = 1; // Handle MMX in DecodeUNPCKLMask()
249 unsigned NumLaneElts = NumElts / NumLanes; in DecodeUNPCKLMask()
282 unsigned NumLanes = NumElts / NumElementsInLane; in decodeVSHUF64x2FamilyMask() local
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/external/v8/src/compiler/
Dsimd-scalar-lowering.cc491 int SimdScalarLowering::NumLanes(SimdType type) { in NumLanes() function in v8::internal::compiler::SimdScalarLowering
511 int num_lanes = NumLanes(type); in GetIndexNodes()
552 int num_lanes = NumLanes(type); in LowerLoadOp()
640 int num_lanes = NumLanes(type); in LowerLoadTransformOp()
743 int num_lanes = NumLanes(rep_type); in LowerStoreOp()
783 int num_lanes = NumLanes(input_rep_type); in LowerBinaryOp()
805 int num_lanes = NumLanes(input_rep_type); in LowerCompareOp()
836 int num_lanes = NumLanes(input_rep_type); in LowerBinaryOpForSmallInt()
900 int num_lanes = NumLanes(input_rep_type); in LowerSaturateBinaryOp()
925 int num_lanes = NumLanes(input_rep_type); in LowerUnaryOp()
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Dsimd-scalar-lowering.h72 int NumLanes(SimdType type);
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86MCInstLower.cpp2101 int NumLanes = 1; in EmitInstruction() local
2104 case X86::VBROADCASTF128: NumLanes = 2; break; in EmitInstruction()
2105 case X86::VBROADCASTI128: NumLanes = 2; break; in EmitInstruction()
2106 case X86::VBROADCASTF32X4Z256rm: NumLanes = 2; break; in EmitInstruction()
2107 case X86::VBROADCASTF32X4rm: NumLanes = 4; break; in EmitInstruction()
2108 case X86::VBROADCASTF32X8rm: NumLanes = 2; break; in EmitInstruction()
2109 case X86::VBROADCASTF64X2Z128rm: NumLanes = 2; break; in EmitInstruction()
2110 case X86::VBROADCASTF64X2rm: NumLanes = 4; break; in EmitInstruction()
2111 case X86::VBROADCASTF64X4rm: NumLanes = 2; break; in EmitInstruction()
2112 case X86::VBROADCASTI32X4Z256rm: NumLanes = 2; break; in EmitInstruction()
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DX86InterleavedAccess.cpp473 unsigned NumLanes = std::max((int)VT.getSizeInBits() / 128, 1); in DecodePALIGNRMask() local
474 unsigned NumLaneElts = NumElts / NumLanes; in DecodePALIGNRMask()
DX86ISelLowering.cpp5717 unsigned NumLanes = VT.getSizeInBits() / 128; in createPackShuffleMask() local
5721 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in createPackShuffleMask()
10575 int NumLanes = Bits / 128; in lowerVectorShuffleAsZeroOrAnyExtend() local
10577 int NumEltsPerLane = NumElements / NumLanes; in lowerVectorShuffleAsZeroOrAnyExtend()
13267 int NumLanes = Size / LaneSize; in lowerVectorShuffleByMerging128BitLanes() local
13268 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles."); in lowerVectorShuffleByMerging128BitLanes()
13272 SmallVector<int, 4> Lanes((unsigned)NumLanes, -1); in lowerVectorShuffleByMerging128BitLanes()
13301 SmallVector<int, 8> LaneMask((unsigned)NumLanes * 2, -1); in lowerVectorShuffleByMerging128BitLanes()
13302 for (int i = 0; i < NumLanes; ++i) in lowerVectorShuffleByMerging128BitLanes()
13474 int NumLanes = VT.getSizeInBits() / 128; in lowerShuffleAsRepeatedMaskAndLanePermute() local
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIMachineFunctionInfo.cpp266 int NumLanes = Size / 4; in allocateSGPRSpillToVGPR() local
272 for (int I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) { in allocateSGPRSpillToVGPR()
/external/capstone/arch/AArch64/
DAArch64InstPrinter.c1149 static void printTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O, unsigned NumLanes, char La… in printTypedVectorList() argument
1155 if (NumLanes) { in printTypedVectorList()
1156 cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, LaneKind); in printTypedVectorList()
1160 switch(NumLanes) { in printTypedVectorList()
1171 switch(NumLanes) { in printTypedVectorList()
1182 switch(NumLanes) { in printTypedVectorList()
1193 switch(NumLanes) { in printTypedVectorList()
1204 switch(NumLanes) { in printTypedVectorList()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/InstCombine/
DInstCombineSimplifyDemanded.cpp1542 unsigned NumLanes = Ty0->getPrimitiveSizeInBits() / 128; in SimplifyDemandedVectorElts() local
1543 unsigned VWidthPerLane = VWidth / NumLanes; in SimplifyDemandedVectorElts()
1544 unsigned InnerVWidthPerLane = InnerVWidth / NumLanes; in SimplifyDemandedVectorElts()
1552 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in SimplifyDemandedVectorElts()
1573 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in SimplifyDemandedVectorElts()
DInstCombineCalls.cpp514 unsigned NumLanes = ResTy->getPrimitiveSizeInBits() / 128; in simplifyX86pack() local
519 unsigned NumDstEltsPerLane = NumDstElts / NumLanes; in simplifyX86pack()
520 unsigned NumSrcEltsPerLane = NumSrcElts / NumLanes; in simplifyX86pack()
532 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyX86pack()
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.h140 template <unsigned NumLanes, char LaneKind>
DAArch64InstPrinter.cpp1337 template <unsigned NumLanes, char LaneKind>
1342 if (NumLanes) in printTypedVectorList()
1343 Suffix += itostr(NumLanes) + LaneKind; in printTypedVectorList()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.h147 template <unsigned NumLanes, char LaneKind>
DAArch64InstPrinter.cpp1269 template <unsigned NumLanes, char LaneKind>
1274 if (NumLanes) in printTypedVectorList()
1275 Suffix += itostr(NumLanes) + LaneKind; in printTypedVectorList()
/external/clang/utils/TableGen/
DNeonEmitter.cpp707 unsigned NumLanes; in fromTypedefName() local
708 Name.substr(0, I).getAsInteger(10, NumLanes); in fromTypedefName()
710 T.Bitwidth = T.ElementBitwidth * NumLanes; in fromTypedefName()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/IR/
DAutoUpgrade.cpp2015 unsigned NumLanes = VT->getPrimitiveSizeInBits() / 128; in UpgradeIntrinsicCall() local
2017 unsigned ControlBitsMask = NumLanes - 1; in UpgradeIntrinsicCall()
2018 unsigned NumControlBits = NumLanes / 2; in UpgradeIntrinsicCall()
2021 for (unsigned l = 0; l != NumLanes; ++l) { in UpgradeIntrinsicCall()
2024 if (l >= NumLanes / 2) in UpgradeIntrinsicCall()
2025 LaneMask += NumLanes; in UpgradeIntrinsicCall()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp7720 int NumLanes = VT.getSizeInBits() / 128; in lowerVectorShuffleAsByteRotate() local
7721 int NumLaneElts = NumElts / NumLanes; in lowerVectorShuffleAsByteRotate()
7789 MVT ByteVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes); in lowerVectorShuffleAsByteRotate()
8227 int NumLanes = Bits / 128; in lowerVectorShuffleAsZeroOrAnyExtend() local
8229 int NumEltsPerLane = NumElements / NumLanes; in lowerVectorShuffleAsZeroOrAnyExtend()
10798 int NumLanes = Size / LaneSize; in lowerVectorShuffleByMerging128BitLanes() local
10799 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles."); in lowerVectorShuffleByMerging128BitLanes()
10803 SmallVector<int, 4> Lanes((unsigned)NumLanes, -1); in lowerVectorShuffleByMerging128BitLanes()
10832 SmallVector<int, 8> LaneMask((unsigned)NumLanes * 2, -1); in lowerVectorShuffleByMerging128BitLanes()
10833 for (int i = 0; i < NumLanes; ++i) in lowerVectorShuffleByMerging128BitLanes()
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/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp10408 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in PerformVCVTCombine() local
10409 if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) { in PerformVCVTCombine()
10428 ISD::INTRINSIC_WO_CHAIN, dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, in PerformVCVTCombine()
10466 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in PerformVDIVCombine() local
10467 if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) { in PerformVDIVCombine()
10486 dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, in PerformVDIVCombine()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMISelLowering.cpp12065 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in PerformVCVTCombine() local
12066 if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) { in PerformVCVTCombine()
12085 ISD::INTRINSIC_WO_CHAIN, dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, in PerformVCVTCombine()
12123 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in PerformVDIVCombine() local
12124 if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) { in PerformVDIVCombine()
12143 dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, in PerformVDIVCombine()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp7722 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in performFpToIntCombine() local
7723 switch (NumLanes) { in performFpToIntCombine()
7793 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in performFDivCombine() local
7794 switch (NumLanes) { in performFDivCombine()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp8879 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in performFpToIntCombine() local
8880 switch (NumLanes) { in performFpToIntCombine()
8952 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in performFDivCombine() local
8953 switch (NumLanes) { in performFDivCombine()