| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_target_nvc0.cpp | 107 { OP_MAD, 0x7, 0x0, 0x0, 0x8, 0x6, 0x2 }, // special c[] constraint
198 OP_ADD, OP_MUL, OP_MAD, OP_FMA, OP_AND, OP_OR, OP_XOR, OP_MAX, OP_MIN, in initOpInfo()
204 OP_ADD, OP_MUL, OP_MAD, OP_FMA, OP_AND, OP_OR, OP_XOR, OP_MAX, OP_MIN in initOpInfo()
543 return (insn->op == OP_ADD) || (insn->op == OP_MAD); in isSatSupported()
619 case OP_MAD: in getThroughput()
651 case OP_MAD: in getThroughput()
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| D | nv50_ir_target_gm107.cpp | 173 if ((insn->op == OP_MUL || insn->op == OP_MAD) && in isBarrierRequired()
218 case OP_MAD: in getLatency()
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| D | nv50_ir_target_nv50.cpp | 90 { OP_MAD, 0x7, 0x0, 0x0, 0x8, 0x6, 0x1, 0x1, 0x0 }, // special constraint
116 OP_ADD, OP_MUL, OP_MAD, OP_FMA, OP_AND, OP_OR, OP_XOR, OP_MAX, OP_MIN, in initOpInfo()
121 OP_MOV, OP_ADD, OP_SUB, OP_MUL, OP_MAD, OP_SAD, OP_RCP, OP_LINTERP, in initOpInfo()
345 if ((i->op == OP_MUL || i->op == OP_MAD) && !isFloatType(i->dType)) { in insnCanLoad()
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| D | nv50_ir_target_gv100.cpp | 35 OP_ADD, OP_MUL, OP_MAD, OP_FMA, OP_MAX, OP_MIN, in initOpInfo()
280 case OP_MAD: in getOpInfo()
417 case OP_MAD: in isSatSupported()
442 if (op == OP_MAD || op == OP_FMA) in isOpSupported()
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| D | nv50_ir_peephole.cpp | 574 case OP_MAD: in expr()
751 case OP_MAD: in expr()
820 case OP_MAD: in expr()
971 case OP_MAD: in opnd3()
1154 case OP_MAD: in opnd()
1273 bld.mkOp3(OP_MAD, TYPE_S32, tA, i->getSrc(0), bld.loadImm(NULL, m), in opnd()
1870 if (!add->precise && prog->getTarget()->isOpSupported(OP_MAD, add->dType)) in handleADD()
1871 changed = tryADDToMADOrSAD(add, OP_MAD); in handleADD()
1887 const Modifier modBad = Modifier(~((toOp == OP_MAD) ? NV50_IR_MOD_NEG : 0)); in tryADDToMADOrSAD()
2538 case OP_MAD: in visit()
[all …]
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| D | nv50_ir_lowering_gv100.cpp | 85 bld.mkOp3(OP_MAD, isSignedType(i->sType) ? TYPE_S64 : TYPE_U64, def, in handleIMAD_HIGH()
113 bld.mkOp3(OP_MAD, i->dType, i->getDef(0), i->getSrc(0), i->getSrc(1), in handleIMUL()
283 case OP_MAD: in visit()
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| D | nv50_ir_from_common.cpp | 94 mkOp3(OP_MAD, TYPE_F32, res[i], clipVtx[c], ucp, res[i]); in handleUserClipPlanes()
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| D | nv50_ir_lowering_nv50.cpp | 102 i[3] = bld->mkOp3(OP_MAD, fTy, t[1], a[1], b[0], t[0]); in expandIntegerMUL()
110 i[4] = bld->mkOp3(OP_MAD, fTy, t[3], a[0], b[0], t[2]); in expandIntegerMUL()
126 i[5] = bld->mkOp3(OP_MAD, fTy, r[4], a[1], b[1], r[2]); in expandIntegerMUL()
463 if (mul->op == OP_MAD) { in handleMUL()
600 case OP_MAD: in visit()
1319 Value *sum = bld.mkOp3v(OP_MAD, TYPE_U16, bld.getSSA(), a[0], b[0], in handleLOAD()
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| D | nv50_ir_lowering_gm107.cpp | 248 bld.mkOp3(OP_MAD , TYPE_U32, tmp0, tmp0, tmp1, tmp2); in handlePFETCH()
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| D | nv50_ir.h | 57 OP_MAD, enumerator
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| D | nv50_ir_from_nir.cpp | 2740 …mkOp3(OP_MAD, TYPE_U32, prmt, getSrc(&insn->src[1]), loadImm(NULL, 0x1111), loadImm(NULL, 0x8880)); in visit()
2748 … mkOp3(OP_MAD, TYPE_U32, prmt, getSrc(&insn->src[1]), loadImm(NULL, 0x22), loadImm(NULL, 0x4410)); in visit()
2756 …mkOp3(OP_MAD, TYPE_U32, prmt, getSrc(&insn->src[1]), loadImm(NULL, 0x2222), loadImm(NULL, 0x9910)); in visit()
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| D | nv50_ir_emit_nvc0.cpp | 2736 case OP_MAD: in emitInstruction()
2965 if (i->predSrc >= 0 && i->op == OP_MAD) in getMinEncodingSize()
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| D | nv50_ir_emit_gv100.cpp | 1790 case OP_MAD: in emitInstruction()
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| D | nv50_ir_emit_nv50.cpp | 1904 case OP_MAD: in emitInstruction()
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| D | nv50_ir_from_tgsi.cpp | 2185 mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp) in buildDot()
3305 mkOp3(OP_MAD, TYPE_F32, dst0[c], in handleInstruction()
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| D | nv50_ir_emit_gk110.cpp | 2560 case OP_MAD: in emitInstruction()
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| D | nv50_ir_ra.cpp | 1537 if (insn->op != OP_MAD && insn->op != OP_FMA && insn->op != OP_SAD) in allocateRegisters()
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| D | nv50_ir_emit_gm107.cpp | 3517 case OP_MAD: in emitInstruction()
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