Home
last modified time | relevance | path

Searched refs:Opc1 (Results 1 – 21 of 21) sorted by relevance

/external/llvm/lib/Target/PowerPC/
DPPCTLSDynamicCall.cpp75 unsigned Opc1, Opc2; in processBlock() local
82 Opc1 = PPC::ADDItlsgdL; in processBlock()
86 Opc1 = PPC::ADDItlsldL; in processBlock()
90 Opc1 = PPC::ADDItlsgdL32; in processBlock()
94 Opc1 = PPC::ADDItlsldL32; in processBlock()
105 MachineInstr *Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3) in processBlock()
DPPCISelDAGToDAG.cpp3058 unsigned Opc1, Opc2, Opc3; in Select() local
3062 Opc1 = PPC::VSPLTISB; in Select()
3067 Opc1 = PPC::VSPLTISH; in Select()
3073 Opc1 = PPC::VSPLTISW; in Select()
3087 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
3100 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
3102 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
3115 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
3117 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCTLSDynamicCall.cpp86 unsigned Opc1, Opc2; in processBlock() local
93 Opc1 = PPC::ADDItlsgdL; in processBlock()
97 Opc1 = PPC::ADDItlsldL; in processBlock()
101 Opc1 = PPC::ADDItlsgdL32; in processBlock()
105 Opc1 = PPC::ADDItlsldL32; in processBlock()
121 MachineInstr *Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3) in processBlock()
DPPCISelDAGToDAG.cpp4856 unsigned Opc1, Opc2, Opc3; in Select() local
4860 Opc1 = PPC::VSPLTISB; in Select()
4865 Opc1 = PPC::VSPLTISH; in Select()
4871 Opc1 = PPC::VSPLTISW; in Select()
4885 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
4897 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
4899 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
4911 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
4913 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
/external/llvm/lib/Target/Mips/
DMips16ISelLowering.h56 MachineBasicBlock *emitSeliT16(unsigned Opc1, unsigned Opc2,
60 MachineBasicBlock *emitSelT16(unsigned Opc1, unsigned Opc2,
DMips16ISelLowering.cpp584 Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr &MI, in emitSelT16() argument
622 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); in emitSelT16()
649 Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2, in emitSeliT16() argument
688 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); in emitSeliT16()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMips16ISelLowering.h56 MachineBasicBlock *emitSeliT16(unsigned Opc1, unsigned Opc2,
60 MachineBasicBlock *emitSelT16(unsigned Opc1, unsigned Opc2,
DMips16ISelLowering.cpp584 Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr &MI, in emitSelT16() argument
622 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); in emitSelT16()
649 Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2, in emitSeliT16() argument
688 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); in emitSeliT16()
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp55 unsigned Opc1 = N1->getMachineOpcode(); in nodesHaveSameOperandValue() local
58 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName); in nodesHaveSameOperandValue()
100 unsigned Opc1 = Load1->getMachineOpcode(); in areLoadsFromSameBasePtr() local
103 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad()) in areLoadsFromSameBasePtr()
106 if (isDS(Opc0) && isDS(Opc1)) { in areLoadsFromSameBasePtr()
124 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1) in areLoadsFromSameBasePtr()
132 if (isSMRD(Opc0) && isSMRD(Opc1)) { in areLoadsFromSameBasePtr()
157 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) { in areLoadsFromSameBasePtr()
167 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset); in areLoadsFromSameBasePtr()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/InstCombine/
DInstCombineVectorOps.cpp1266 BinaryOperator::BinaryOps Opc1 = B1->getOpcode(); in foldSelectShuffle() local
1268 if (ConstantsAreOp1 && Opc0 != Opc1) { in foldSelectShuffle()
1272 if (Opc0 == Instruction::Shl || Opc1 == Instruction::Shl) in foldSelectShuffle()
1280 Opc1 = AltB1.Opcode; in foldSelectShuffle()
1285 if (Opc0 != Opc1) in foldSelectShuffle()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp112 unsigned Opc1 = N1->getMachineOpcode(); in nodesHaveSameOperandValue() local
115 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName); in nodesHaveSameOperandValue()
157 unsigned Opc1 = Load1->getMachineOpcode(); in areLoadsFromSameBasePtr() local
160 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad()) in areLoadsFromSameBasePtr()
163 if (isDS(Opc0) && isDS(Opc1)) { in areLoadsFromSameBasePtr()
181 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1) in areLoadsFromSameBasePtr()
189 if (isSMRD(Opc0) && isSMRD(Opc1)) { in areLoadsFromSameBasePtr()
192 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::sbase) == -1) in areLoadsFromSameBasePtr()
219 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) { in areLoadsFromSameBasePtr()
229 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset); in areLoadsFromSameBasePtr()
/external/llvm/include/llvm/IR/
DPatternMatch.h635 template <typename LHS_t, typename RHS_t, unsigned Opc1, unsigned Opc2>
643 if (V->getValueID() == Value::InstructionVal + Opc1 || in match()
649 return (CE->getOpcode() == Opc1 || CE->getOpcode() == Opc2) && in match()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrInfo.cpp5631 unsigned Opc1 = Load1->getMachineOpcode(); in areLoadsFromSameBasePtr() local
5633 switch (Opc1) { in areLoadsFromSameBasePtr()
5820 unsigned Opc1 = Load1->getMachineOpcode(); in shouldScheduleLoadsNear() local
5822 if (Opc1 != Opc2) in shouldScheduleLoadsNear()
5825 switch (Opc1) { in shouldScheduleLoadsNear()
DX86IntrinsicsInfo.h46 uint16_t Opc1; member
DX86ISelLowering.cpp20479 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
20499 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
20523 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
20552 assert(IntrData->Opc1 == 0 && "Unexpected second opcode!"); in LowerINTRINSIC_WO_CHAIN()
20564 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
20582 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
20645 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
20684 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
20706 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
20745 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
[all …]
/external/llvm/lib/Target/X86/
DX86InstrInfo.cpp6614 unsigned Opc1 = Load1->getMachineOpcode(); in areLoadsFromSameBasePtr() local
6616 switch (Opc1) { in areLoadsFromSameBasePtr()
6722 unsigned Opc1 = Load1->getMachineOpcode(); in shouldScheduleLoadsNear() local
6724 if (Opc1 != Opc2) in shouldScheduleLoadsNear()
6727 switch (Opc1) { in shouldScheduleLoadsNear()
DX86ISelLowering.cpp17382 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
17400 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
17432 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0; in LowerINTRINSIC_WO_CHAIN()
17457 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
17543 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
17611 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
17717 if (IntrData->Opc1 != 0) { in LowerINTRINSIC_WO_CHAIN()
17721 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
17750 if (IntrData->Opc1 != 0) { in LowerINTRINSIC_WO_CHAIN()
17754 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd); in LowerINTRINSIC_WO_CHAIN()
[all …]
DX86IntrinsicsInfo.h46 uint16_t Opc1; member
/external/clang/lib/CodeGen/
DCGBuiltin.cpp4036 Value *Opc1 = EmitScalarExpr(E->getArg(1)); in EmitARMBuiltinExpr() local
4045 return Builder.CreateCall(F, {Coproc, Opc1, Rt, Rt2, CRm}); in EmitARMBuiltinExpr()
4063 Value *Opc1 = EmitScalarExpr(E->getArg(1)); in EmitARMBuiltinExpr() local
4065 Value *RtAndRt2 = Builder.CreateCall(F, {Coproc, Opc1, CRm}); in EmitARMBuiltinExpr()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp421 unsigned Opc1 = Is64Bit ? AArch64::MOVi64imm : AArch64::MOVi32imm; in materializeFP() local
426 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc1), TmpReg) in materializeFP()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp375 unsigned Opc1 = Is64Bit ? AArch64::MOVi64imm : AArch64::MOVi32imm; in materializeFP() local
380 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc1), TmpReg) in materializeFP()