/external/smali/dexlib2/src/main/java/org/jf/dexlib2/ |
D | Opcode.java | 42 public enum Opcode enum 44 NOP(0x00, "nop", ReferenceType.NONE, Format.Format10x, Opcode.CAN_CONTINUE), 45 …MOVE(0x01, "move", ReferenceType.NONE, Format.Format12x, Opcode.CAN_CONTINUE | Opcode.SETS_REGISTE… 46 …16(0x02, "move/from16", ReferenceType.NONE, Format.Format22x, Opcode.CAN_CONTINUE | Opcode.SETS_RE… 47 …MOVE_16(0x03, "move/16", ReferenceType.NONE, Format.Format32x, Opcode.CAN_CONTINUE | Opcode.SETS_R… 48 …"move-wide", ReferenceType.NONE, Format.Format12x, Opcode.CAN_CONTINUE | Opcode.SETS_REGISTER | Op… 49 …ide/from16", ReferenceType.NONE, Format.Format22x, Opcode.CAN_CONTINUE | Opcode.SETS_REGISTER | Op… 50 …ve-wide/16", ReferenceType.NONE, Format.Format32x, Opcode.CAN_CONTINUE | Opcode.SETS_REGISTER | Op… 51 …CT(0x07, "move-object", ReferenceType.NONE, Format.Format12x, Opcode.CAN_CONTINUE | Opcode.SETS_RE… 52 …, "move-object/from16", ReferenceType.NONE, Format.Format22x, Opcode.CAN_CONTINUE | Opcode.SETS_RE… [all …]
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/external/smali/dexlib2/src/main/java/org/jf/dexlib2/analysis/ |
D | OdexedFieldInstructionMapper.java | 34 import org.jf.dexlib2.Opcode; 56 @Nonnull public final Opcode normalOpcode; 57 @Nullable public final Opcode quickOpcode; 58 @Nullable public final Opcode volatileOpcode; 60 public FieldOpcode(char type, @Nonnull Opcode normalOpcode, @Nullable Opcode quickOpcode, in FieldOpcode() 61 @Nullable Opcode volatileOpcode) { in FieldOpcode() 69 …public FieldOpcode(char type, boolean isStatic, @Nonnull Opcode normalOpcode, @Nullable Opcode vol… in FieldOpcode() 77 public FieldOpcode(char type, @Nonnull Opcode normalOpcode, @Nullable Opcode quickOpcode) { in FieldOpcode() 87 new FieldOpcode('Z', Opcode.IGET_BOOLEAN, Opcode.IGET_QUICK, Opcode.IGET_VOLATILE), 88 new FieldOpcode('B', Opcode.IGET_BYTE, Opcode.IGET_QUICK, Opcode.IGET_VOLATILE), [all …]
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/external/mesa3d/src/gallium/drivers/r300/compiler/ |
D | radeon_opcodes.c | 35 .Opcode = RC_OPCODE_NOP, 39 .Opcode = RC_OPCODE_ILLEGAL_OPCODE, 43 .Opcode = RC_OPCODE_ABS, 50 .Opcode = RC_OPCODE_ADD, 57 .Opcode = RC_OPCODE_ARL, 63 .Opcode = RC_OPCODE_ARR, 69 .Opcode = RC_OPCODE_CEIL, 76 .Opcode = RC_OPCODE_CLAMP, 83 .Opcode = RC_OPCODE_CMP, 90 .Opcode = RC_OPCODE_CND, [all …]
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/external/swiftshader/third_party/subzero/src/ |
D | IceAssemblerMIPS32.cpp | 207 void AssemblerMIPS32::emitRsRt(IValueT Opcode, const Operand *OpRs, in emitRsRt() argument 212 Opcode |= Rs << 21; in emitRsRt() 213 Opcode |= Rt << 16; in emitRsRt() 215 emitInst(Opcode); in emitRsRt() 218 void AssemblerMIPS32::emitRtRsImm16(IValueT Opcode, const Operand *OpRt, in emitRtRsImm16() argument 224 Opcode |= Rs << 21; in emitRtRsImm16() 225 Opcode |= Rt << 16; in emitRtRsImm16() 226 Opcode |= Imm & 0xffff; in emitRtRsImm16() 228 emitInst(Opcode); in emitRtRsImm16() 231 void AssemblerMIPS32::emitRtRsImm16Rel(IValueT Opcode, const Operand *OpRt, in emitRtRsImm16Rel() argument [all …]
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/external/smali/smalidea/src/main/java/org/jf/smalidea/findUsages/ |
D | SmaliUsageTypeProvider.java | 40 import org.jf.dexlib2.Opcode; 74 …private final Set<Opcode> newArrayInstructions = EnumSet.of(Opcode.FILLED_NEW_ARRAY, Opcode.NEW_AR… 75 Opcode.FILLED_NEW_ARRAY_RANGE); 77 …private final Set<Opcode> fieldReadInstructions = EnumSet.of(Opcode.IGET, Opcode.IGET_BOOLEAN, Opc… 78 …Opcode.IGET_CHAR, Opcode.IGET_OBJECT, Opcode.IGET_OBJECT_VOLATILE, Opcode.IGET_SHORT, Opcode.IGET_… 79 … Opcode.IGET_WIDE, Opcode.IGET_WIDE_VOLATILE, Opcode.SGET, Opcode.SGET_BOOLEAN, Opcode.SGET_BYTE, 80 …Opcode.SGET_CHAR, Opcode.SGET_OBJECT, Opcode.SGET_OBJECT_VOLATILE, Opcode.SGET_SHORT, Opcode.SGET_… 81 Opcode.SGET_WIDE, Opcode.SGET_WIDE_VOLATILE); 83 …private final Set<Opcode> fieldWriteInstructions = EnumSet.of(Opcode.IPUT, Opcode.IPUT_BOOLEAN, Op… 84 …Opcode.IPUT_CHAR, Opcode.IPUT_OBJECT, Opcode.IPUT_OBJECT_VOLATILE, Opcode.IPUT_SHORT, Opcode.IPUT_… [all …]
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/external/capstone/arch/XCore/ |
D | XCoreGenDisassemblerTables.inc | 32 /* 15 */ MCD_OPC_Decode, 241, 1, 0, // Opcode: WAITEU_0R 34 /* 24 */ MCD_OPC_Decode, 57, 0, // Opcode: CLRE_0R 36 /* 32 */ MCD_OPC_Decode, 216, 1, 0, // Opcode: SSYNC_0r 38 /* 41 */ MCD_OPC_Decode, 91, 0, // Opcode: FREET_0R 40 /* 49 */ MCD_OPC_Decode, 66, 0, // Opcode: DCALL_0R 42 /* 57 */ MCD_OPC_Decode, 123, 0, // Opcode: KRET_0R 44 /* 65 */ MCD_OPC_Decode, 72, 0, // Opcode: DRET_0R 46 /* 73 */ MCD_OPC_Decode, 197, 1, 0, // Opcode: SETKEP_0R 49 /* 84 */ MCD_OPC_Decode, 75, 1, // Opcode: EDU_1r 51 /* 91 */ MCD_OPC_Decode, 78, 1, // Opcode: EEU_1r [all …]
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/external/smali/dexlib2/src/test/java/org/jf/dexlib2/builder/ |
D | PayloadAlignmentTest.java | 35 import org.jf.dexlib2.Opcode; 53 implBuilder.addInstruction(new BuilderInstruction10x(Opcode.NOP)); in testPayloadAlignmentRemoveNop() 63 Assert.assertEquals(instruction.getOpcode(), Opcode.ARRAY_PAYLOAD); in testPayloadAlignmentRemoveNop() 70 implBuilder.addInstruction(new BuilderInstruction12x(Opcode.MOVE, 0, 0)); in testPayloadAlignmentAddNop() 79 Assert.assertEquals(instruction.getOpcode(), Opcode.MOVE); in testPayloadAlignmentAddNop() 82 Assert.assertEquals(instruction.getOpcode(), Opcode.NOP); in testPayloadAlignmentAddNop() 85 Assert.assertEquals(instruction.getOpcode(), Opcode.ARRAY_PAYLOAD); in testPayloadAlignmentAddNop() 93 implBuilder.addInstruction(new BuilderInstruction31t(Opcode.FILL_ARRAY_DATA, 0, label)); in testPayloadAlignmentRemoveNopWithReferent() 94 implBuilder.addInstruction(new BuilderInstruction12x(Opcode.MOVE, 0, 0)); in testPayloadAlignmentRemoveNopWithReferent() 95 implBuilder.addInstruction(new BuilderInstruction12x(Opcode.MOVE, 0, 0)); in testPayloadAlignmentRemoveNopWithReferent() [all …]
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/external/capstone/arch/PowerPC/ |
D | PPCGenDisassemblerTables.inc | 34 /* 7 */ MCD_OPC_Decode, 161, 7, 0, // Opcode: TDI 36 /* 15 */ MCD_OPC_Decode, 178, 7, 1, // Opcode: TWI 42 /* 37 */ MCD_OPC_Decode, 186, 7, 2, // Opcode: VADDUBM 44 /* 45 */ MCD_OPC_Decode, 188, 7, 2, // Opcode: VADDUHM 46 /* 53 */ MCD_OPC_Decode, 190, 7, 2, // Opcode: VADDUWM 48 /* 61 */ MCD_OPC_Decode, 181, 7, 2, // Opcode: VADDCUW 50 /* 69 */ MCD_OPC_Decode, 187, 7, 2, // Opcode: VADDUBS 52 /* 77 */ MCD_OPC_Decode, 189, 7, 2, // Opcode: VADDUHS 54 /* 85 */ MCD_OPC_Decode, 191, 7, 2, // Opcode: VADDUWS 56 /* 93 */ MCD_OPC_Decode, 183, 7, 2, // Opcode: VADDSBS [all …]
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/external/capstone/arch/Sparc/ |
D | SparcGenDisassemblerTables.inc | 33 /* 20 */ MCD_OPC_Decode, 209, 3, 0, // Opcode: UNIMP 40 /* 46 */ MCD_OPC_Decode, 92, 1, // Opcode: BPICCNT 43 /* 57 */ MCD_OPC_Decode, 91, 1, // Opcode: BPICCANT 48 /* 75 */ MCD_OPC_Decode, 89, 1, // Opcode: BPICC 51 /* 86 */ MCD_OPC_Decode, 90, 1, // Opcode: BPICCA 55 /* 100 */ MCD_OPC_Decode, 108, 1, // Opcode: BPXCCNT 57 /* 107 */ MCD_OPC_Decode, 107, 1, // Opcode: BPXCCANT 61 /* 121 */ MCD_OPC_Decode, 105, 1, // Opcode: BPXCC 63 /* 128 */ MCD_OPC_Decode, 106, 1, // Opcode: BPXCCA 68 /* 148 */ MCD_OPC_Decode, 71, 0, // Opcode: BA [all …]
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/external/capstone/arch/Mips/ |
D | MipsGenDisassemblerTables.inc | 33 /* 11 */ MCD_OPC_Decode, 189, 7, 10, // Opcode: LWC3 36 /* 23 */ MCD_OPC_Decode, 139, 7, 10, // Opcode: LDC3 39 /* 35 */ MCD_OPC_Decode, 174, 12, 10, // Opcode: SWC3 42 /* 47 */ MCD_OPC_Decode, 227, 10, 10, // Opcode: SDC3 56 /* 25 */ MCD_OPC_Decode, 174, 11, 14, // Opcode: SLL_MM 59 /* 37 */ MCD_OPC_Decode, 241, 11, 14, // Opcode: SRL_MM 62 /* 49 */ MCD_OPC_Decode, 221, 11, 14, // Opcode: SRA_MM 65 /* 61 */ MCD_OPC_Decode, 191, 10, 14, // Opcode: ROTR_MM 68 /* 73 */ MCD_OPC_Decode, 155, 2, 15, // Opcode: BREAK_MM 71 /* 85 */ MCD_OPC_Decode, 225, 6, 16, // Opcode: INS_MM [all …]
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/external/capstone/arch/SystemZ/ |
D | SystemZGenDisassemblerTables.inc | 32 /* 14 */ MCD_OPC_Decode, 242, 2, 0, // Opcode: AsmOBR 34 /* 22 */ MCD_OPC_Decode, 162, 1, 0, // Opcode: AsmHBR 36 /* 30 */ MCD_OPC_Decode, 207, 2, 0, // Opcode: AsmNLEBR 38 /* 38 */ MCD_OPC_Decode, 148, 2, 0, // Opcode: AsmLBR 40 /* 46 */ MCD_OPC_Decode, 189, 2, 0, // Opcode: AsmNHEBR 42 /* 54 */ MCD_OPC_Decode, 158, 2, 0, // Opcode: AsmLHBR 44 /* 62 */ MCD_OPC_Decode, 179, 2, 0, // Opcode: AsmNEBR 46 /* 70 */ MCD_OPC_Decode, 153, 1, 0, // Opcode: AsmEBR 48 /* 78 */ MCD_OPC_Decode, 216, 2, 0, // Opcode: AsmNLHBR 50 /* 86 */ MCD_OPC_Decode, 163, 1, 0, // Opcode: AsmHEBR [all …]
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/external/smali/dexlib2/src/test/java/org/jf/dexlib2/util/ |
D | InstructionOffsetMapTest.java | 36 import org.jf.dexlib2.Opcode; 48 /*00: 0x00*/ new ImmutableInstruction10t(Opcode.GOTO, 1), in testInstructionOffsetMap() 49 /*01: 0x01*/ new ImmutableInstruction10x(Opcode.NOP), in testInstructionOffsetMap() 50 /*02: 0x02*/ new ImmutableInstruction11n(Opcode.CONST_4, 2, 3), in testInstructionOffsetMap() 51 /*03: 0x03*/ new ImmutableInstruction11x(Opcode.RETURN, 4), in testInstructionOffsetMap() 52 /*04: 0x04*/ new ImmutableInstruction12x(Opcode.ARRAY_LENGTH, 5, 6), in testInstructionOffsetMap() 53 /*05: 0x05*/ new ImmutableInstruction20t(Opcode.GOTO_16, 7), in testInstructionOffsetMap() 54 …/*06: 0x07*/ new ImmutableInstruction21c(Opcode.CONST_STRING, 8, new ImmutableStringReference("bla… in testInstructionOffsetMap() 55 /*07: 0x09*/ new ImmutableInstruction21ih(Opcode.CONST_HIGH16, 9, 0x10000), in testInstructionOffsetMap() 56 … /*08: 0x0b*/ new ImmutableInstruction21lh(Opcode.CONST_WIDE_HIGH16, 10, 0x1000000000000L), in testInstructionOffsetMap() [all …]
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/external/swiftshader/third_party/SPIRV-Tools/utils/vscode/src/schema/ |
D | schema.go | 21 type Opcode struct { struct 24 Opcode int member 100 type OpcodeMap map[string]*Opcode 921 OpNop = &Opcode { 924 Opcode: 0, 928 OpUndef = &Opcode { 931 Opcode: 1, 945 OpSourceContinued = &Opcode { 948 Opcode: 2, 957 OpSource = &Opcode { [all …]
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/external/deqp-deps/SPIRV-Tools/utils/vscode/src/schema/ |
D | schema.go | 21 type Opcode struct { struct 24 Opcode int member 100 type OpcodeMap map[string]*Opcode 921 OpNop = &Opcode { 924 Opcode: 0, 928 OpUndef = &Opcode { 931 Opcode: 1, 945 OpSourceContinued = &Opcode { 948 Opcode: 2, 957 OpSource = &Opcode { [all …]
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/external/angle/third_party/spirv-tools/src/utils/vscode/src/schema/ |
D | schema.go | 21 type Opcode struct { struct 24 Opcode int argument 100 type OpcodeMap map[string]*Opcode 921 OpNop = &Opcode { 924 Opcode: 0, 928 OpUndef = &Opcode { 931 Opcode: 1, 945 OpSourceContinued = &Opcode { 948 Opcode: 2, 957 OpSource = &Opcode { [all …]
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/external/capstone/arch/AArch64/ |
D | AArch64GenDisassemblerTables.inc | 38 /* 35 */ MCD_OPC_Decode, 145, 15, 0, // Opcode: STXRB 40 /* 43 */ MCD_OPC_Decode, 189, 14, 0, // Opcode: STLXRB 44 /* 58 */ MCD_OPC_Decode, 169, 8, 0, // Opcode: LDXRB 46 /* 66 */ MCD_OPC_Decode, 169, 7, 0, // Opcode: LDAXRB 49 /* 80 */ MCD_OPC_Decode, 183, 14, 0, // Opcode: STLRB 52 /* 94 */ MCD_OPC_Decode, 163, 7, 0, // Opcode: LDARB 56 /* 109 */ MCD_OPC_Decode, 93, 1, // Opcode: ANDWrs 58 /* 116 */ MCD_OPC_Decode, 109, 1, // Opcode: BICWrs 62 /* 130 */ MCD_OPC_Decode, 62, 1, // Opcode: ADDWrs 65 /* 143 */ MCD_OPC_Decode, 63, 2, // Opcode: ADDWrx [all …]
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/external/smali/dexlib2/src/main/java/org/jf/dexlib2/writer/ |
D | InstructionFactory.java | 35 import org.jf.dexlib2.Opcode; 45 Instruction makeInstruction10t(@Nonnull Opcode opcode, int codeOffset); in makeInstruction10t() 46 Instruction makeInstruction10x(@Nonnull Opcode opcode); in makeInstruction10x() 47 Instruction makeInstruction11n(@Nonnull Opcode opcode, int registerA, int literal); in makeInstruction11n() 48 Instruction makeInstruction11x(@Nonnull Opcode opcode, int registerA); in makeInstruction11x() 49 Instruction makeInstruction12x(@Nonnull Opcode opcode, int registerA, int registerB); in makeInstruction12x() 50 …Instruction makeInstruction20bc(@Nonnull Opcode opcode, int verificationError, @Nonnull Ref refere… in makeInstruction20bc() 51 Instruction makeInstruction20t(@Nonnull Opcode opcode, int codeOffset); in makeInstruction20t() 52 Instruction makeInstruction21c(@Nonnull Opcode opcode, int registerA, @Nonnull Ref reference); in makeInstruction21c() 53 Instruction makeInstruction21ih(@Nonnull Opcode opcode, int registerA, int literal); in makeInstruction21ih() [all …]
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/ |
D | PPCGenDisassemblerTables.inc | 39 /* 16 */ MCD::OPC_Decode, 189, 2, 0, // Opcode: ATTN 41 /* 25 */ MCD::OPC_Decode, 165, 12, 1, // Opcode: TDI 43 /* 34 */ MCD::OPC_Decode, 186, 12, 2, // Opcode: TWI 49 /* 59 */ MCD::OPC_Decode, 200, 12, 3, // Opcode: VADDUBM 51 /* 68 */ MCD::OPC_Decode, 203, 12, 3, // Opcode: VADDUHM 53 /* 77 */ MCD::OPC_Decode, 206, 12, 3, // Opcode: VADDUWM 55 /* 86 */ MCD::OPC_Decode, 202, 12, 3, // Opcode: VADDUDM 57 /* 95 */ MCD::OPC_Decode, 205, 12, 3, // Opcode: VADDUQM 59 /* 104 */ MCD::OPC_Decode, 192, 12, 3, // Opcode: VADDCUQ 61 /* 113 */ MCD::OPC_Decode, 193, 12, 3, // Opcode: VADDCUW [all …]
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/external/capstone/arch/ARM/ |
D | ARMGenDisassemblerTables.inc | 40 /* 45 */ MCD_OPC_Decode, 41, 0, // Opcode: ANDrr 42 /* 52 */ MCD_OPC_Decode, 42, 1, // Opcode: ANDrsi 46 /* 69 */ MCD_OPC_Decode, 198, 3, 0, // Opcode: SUBrr 48 /* 77 */ MCD_OPC_Decode, 199, 3, 1, // Opcode: SUBrsi 52 /* 95 */ MCD_OPC_Decode, 30, 0, // Opcode: ADDrr 54 /* 102 */ MCD_OPC_Decode, 31, 1, // Opcode: ADDrsi 58 /* 119 */ MCD_OPC_Decode, 179, 2, 0, // Opcode: SBCrr 60 /* 127 */ MCD_OPC_Decode, 180, 2, 1, // Opcode: SBCrsi 67 /* 153 */ MCD_OPC_Decode, 43, 2, // Opcode: ANDrsr 70 /* 164 */ MCD_OPC_Decode, 200, 3, 2, // Opcode: SUBrsr [all …]
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/external/llvm/lib/Target/AMDGPU/ |
D | SIInstrInfo.h | 42 static BranchPredicate getBranchPredicate(unsigned Opcode); 63 MachineInstr &Inst, unsigned Opcode) const; 66 MachineInstr &Inst, unsigned Opcode) const; 187 bool isSALU(uint16_t Opcode) const { in isSALU() argument 188 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU() 195 bool isVALU(uint16_t Opcode) const { in isVALU() argument 196 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU() 203 bool isVMEM(uint16_t Opcode) const { in isVMEM() argument 204 return isMUBUF(Opcode) || isMTBUF(Opcode) || isMIMG(Opcode); in isVMEM() 211 bool isSOP1(uint16_t Opcode) const { in isSOP1() argument [all …]
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
D | MipsGenDisassemblerTables.inc | 39 /* 13 */ MCD::OPC_Decode, 196, 6, 0, // Opcode: Bimm16 42 /* 27 */ MCD::OPC_Decode, 194, 6, 1, // Opcode: BeqzRxImm16 45 /* 41 */ MCD::OPC_Decode, 198, 6, 1, // Opcode: BnezRxImm16 48 /* 55 */ MCD::OPC_Decode, 129, 5, 2, // Opcode: AddiuRxRxImm16 51 /* 69 */ MCD::OPC_Decode, 221, 19, 1, // Opcode: SltiRxImm16 54 /* 83 */ MCD::OPC_Decode, 223, 19, 1, // Opcode: SltiuRxImm16 59 /* 105 */ MCD::OPC_Decode, 201, 6, 0, // Opcode: Bteqz16 62 /* 119 */ MCD::OPC_Decode, 203, 6, 0, // Opcode: Btnez16 65 /* 133 */ MCD::OPC_Decode, 132, 5, 0, // Opcode: AddiuSpImm16 68 /* 147 */ MCD::OPC_Decode, 235, 15, 3, // Opcode: Move32R16 [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
D | SIInstrInfo.h | 64 static BranchPredicate getBranchPredicate(unsigned Opcode); 92 MachineInstr &Inst, unsigned Opcode) const; 98 MachineInstr &Inst, unsigned Opcode) const; 304 bool isSALU(uint16_t Opcode) const { in isSALU() argument 305 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU() 312 bool isVALU(uint16_t Opcode) const { in isVALU() argument 313 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU() 320 bool isVMEM(uint16_t Opcode) const { in isVMEM() argument 321 return isMUBUF(Opcode) || isMTBUF(Opcode) || isMIMG(Opcode); in isVMEM() 328 bool isSOP1(uint16_t Opcode) const { in isSOP1() argument [all …]
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
D | AArch64GenDisassemblerTables.inc | 51 /* 61 */ MCD::OPC_Decode, 185, 1, 0, // Opcode: ADD_ZPmZ_B 54 /* 75 */ MCD::OPC_Decode, 187, 1, 0, // Opcode: ADD_ZPmZ_H 59 /* 97 */ MCD::OPC_Decode, 247, 29, 0, // Opcode: SUB_ZPmZ_B 62 /* 111 */ MCD::OPC_Decode, 249, 29, 0, // Opcode: SUB_ZPmZ_H 67 /* 133 */ MCD::OPC_Decode, 221, 29, 0, // Opcode: SUBR_ZPmZ_B 70 /* 147 */ MCD::OPC_Decode, 223, 29, 0, // Opcode: SUBR_ZPmZ_H 75 /* 169 */ MCD::OPC_Decode, 196, 23, 0, // Opcode: SMAX_ZPmZ_B 78 /* 183 */ MCD::OPC_Decode, 198, 23, 0, // Opcode: SMAX_ZPmZ_H 83 /* 205 */ MCD::OPC_Decode, 252, 31, 0, // Opcode: UMAX_ZPmZ_B 86 /* 219 */ MCD::OPC_Decode, 254, 31, 0, // Opcode: UMAX_ZPmZ_H [all …]
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/external/llvm/lib/Target/NVPTX/ |
D | NVPTXISelDAGToDAG.cpp | 738 unsigned Opcode; in tryLoad() local 744 Opcode = NVPTX::LD_i8_avar; in tryLoad() 747 Opcode = NVPTX::LD_i16_avar; in tryLoad() 750 Opcode = NVPTX::LD_i32_avar; in tryLoad() 753 Opcode = NVPTX::LD_i64_avar; in tryLoad() 756 Opcode = NVPTX::LD_f32_avar; in tryLoad() 759 Opcode = NVPTX::LD_f64_avar; in tryLoad() 767 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops); in tryLoad() 772 Opcode = NVPTX::LD_i8_asi; in tryLoad() 775 Opcode = NVPTX::LD_i16_asi; in tryLoad() [all …]
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/external/smali/dexlib2/src/main/java/org/jf/dexlib2/immutable/instruction/ |
D | ImmutableInstructionFactory.java | 34 import org.jf.dexlib2.Opcode; 49 public ImmutableInstruction10t makeInstruction10t(@Nonnull Opcode opcode, in makeInstruction10t() 54 public ImmutableInstruction10x makeInstruction10x(@Nonnull Opcode opcode) { in makeInstruction10x() 58 public ImmutableInstruction11n makeInstruction11n(@Nonnull Opcode opcode, in makeInstruction11n() 64 public ImmutableInstruction11x makeInstruction11x(@Nonnull Opcode opcode, in makeInstruction11x() 69 public ImmutableInstruction12x makeInstruction12x(@Nonnull Opcode opcode, in makeInstruction12x() 75 public ImmutableInstruction20bc makeInstruction20bc(@Nonnull Opcode opcode, in makeInstruction20bc() 81 public ImmutableInstruction20t makeInstruction20t(@Nonnull Opcode opcode, in makeInstruction20t() 86 public ImmutableInstruction21c makeInstruction21c(@Nonnull Opcode opcode, in makeInstruction21c() 92 public ImmutableInstruction21ih makeInstruction21ih(@Nonnull Opcode opcode, in makeInstruction21ih() [all …]
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