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Searched refs:Ops (Results 1 – 25 of 455) sorted by relevance

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/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.cpp764 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl), in tryLoad() local
767 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops); in tryLoad()
792 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl), in tryLoad() local
795 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops); in tryLoad()
845 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl), in tryLoad() local
848 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops); in tryLoad()
897 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl), in tryLoad() local
900 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops); in tryLoad()
1029 SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL), in tryLoadVector() local
1032 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops); in tryLoadVector()
[all …]
/external/clang/lib/CodeGen/
DCGBuiltin.cpp2572 Value *CodeGenFunction::EmitNeonCall(Function *F, SmallVectorImpl<Value*> &Ops, in EmitNeonCall() argument
2579 Ops[j] = EmitNeonShiftVector(Ops[j], ai->getType(), rightshift); in EmitNeonCall()
2581 Ops[j] = Builder.CreateBitCast(Ops[j], ai->getType(), name); in EmitNeonCall()
2583 return Builder.CreateCall(F, Ops, name); in EmitNeonCall()
3273 SmallVectorImpl<Value *> &Ops, in EmitCommonNeonSISDBuiltinExpr() argument
3296 std::swap(Ops[0], Ops[1]); in EmitCommonNeonSISDBuiltinExpr()
3312 if (Ops[j]->getType()->getPrimitiveSizeInBits() == in EmitCommonNeonSISDBuiltinExpr()
3316 assert(ArgTy->isVectorTy() && !Ops[j]->getType()->isVectorTy()); in EmitCommonNeonSISDBuiltinExpr()
3319 Ops[j] = in EmitCommonNeonSISDBuiltinExpr()
3320 CGF.Builder.CreateTruncOrBitCast(Ops[j], ArgTy->getVectorElementType()); in EmitCommonNeonSISDBuiltinExpr()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/FuzzMutate/
DOperations.cpp19 void llvm::describeFuzzerIntOps(std::vector<fuzzerop::OpDescriptor> &Ops) { in describeFuzzerIntOps() argument
20 Ops.push_back(binOpDescriptor(1, Instruction::Add)); in describeFuzzerIntOps()
21 Ops.push_back(binOpDescriptor(1, Instruction::Sub)); in describeFuzzerIntOps()
22 Ops.push_back(binOpDescriptor(1, Instruction::Mul)); in describeFuzzerIntOps()
23 Ops.push_back(binOpDescriptor(1, Instruction::SDiv)); in describeFuzzerIntOps()
24 Ops.push_back(binOpDescriptor(1, Instruction::UDiv)); in describeFuzzerIntOps()
25 Ops.push_back(binOpDescriptor(1, Instruction::SRem)); in describeFuzzerIntOps()
26 Ops.push_back(binOpDescriptor(1, Instruction::URem)); in describeFuzzerIntOps()
27 Ops.push_back(binOpDescriptor(1, Instruction::Shl)); in describeFuzzerIntOps()
28 Ops.push_back(binOpDescriptor(1, Instruction::LShr)); in describeFuzzerIntOps()
[all …]
/external/llvm/lib/Transforms/Scalar/
DReassociate.cpp57 static void PrintOps(Instruction *I, const SmallVectorImpl<ValueEntry> &Ops) { in PrintOps() argument
60 << *Ops[0].Op->getType() << '\t'; in PrintOps()
61 for (unsigned i = 0, e = Ops.size(); i != e; ++i) { in PrintOps()
63 Ops[i].Op->printAsOperand(dbgs(), false, M); in PrintOps()
64 dbgs() << ", #" << Ops[i].Rank << "] "; in PrintOps()
434 SmallVectorImpl<RepeatedValue> &Ops) { in LinearizeExprTree() argument
594 Ops.push_back(std::make_pair(V, Weight)); in LinearizeExprTree()
600 if (Ops.empty()) { in LinearizeExprTree()
603 Ops.emplace_back(Identity, APInt(Bitwidth, 1)); in LinearizeExprTree()
612 SmallVectorImpl<ValueEntry> &Ops) { in RewriteExprTree() argument
[all …]
DFloat2Int.cpp252 Op = [](ArrayRef<ConstantRange> Ops) { in walkForwards() argument
253 assert(Ops.size() == 2 && "FAdd is a binary operator!"); in walkForwards()
254 return Ops[0].add(Ops[1]); in walkForwards()
259 Op = [](ArrayRef<ConstantRange> Ops) { in walkForwards() argument
260 assert(Ops.size() == 2 && "FSub is a binary operator!"); in walkForwards()
261 return Ops[0].sub(Ops[1]); in walkForwards()
266 Op = [](ArrayRef<ConstantRange> Ops) { in walkForwards() argument
267 assert(Ops.size() == 2 && "FMul is a binary operator!"); in walkForwards()
268 return Ops[0].multiply(Ops[1]); in walkForwards()
278 Op = [](ArrayRef<ConstantRange> Ops) { in walkForwards() argument
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Scalar/
DReassociate.cpp75 static void PrintOps(Instruction *I, const SmallVectorImpl<ValueEntry> &Ops) { in PrintOps() argument
78 << *Ops[0].Op->getType() << '\t'; in PrintOps()
79 for (unsigned i = 0, e = Ops.size(); i != e; ++i) { in PrintOps()
81 Ops[i].Op->printAsOperand(dbgs(), false, M); in PrintOps()
82 dbgs() << ", #" << Ops[i].Rank << "] "; in PrintOps()
448 SmallVectorImpl<RepeatedValue> &Ops) { in LinearizeExprTree() argument
611 Ops.push_back(std::make_pair(V, Weight)); in LinearizeExprTree()
617 if (Ops.empty()) { in LinearizeExprTree()
620 Ops.emplace_back(Identity, APInt(Bitwidth, 1)); in LinearizeExprTree()
629 SmallVectorImpl<ValueEntry> &Ops) { in RewriteExprTree() argument
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/
DPPCGenDAGISel.inc79 3/*#Ops*/, 1, 3, 4,
88 MVT::v16i8, 3/*#Ops*/, 1, 1, 5, // Results = #6
90 3/*#Ops*/, 6, 3, 4,
106 3/*#Ops*/, 1, 3, 4,
115 MVT::v16i8, 3/*#Ops*/, 1, 1, 5, // Results = #6
117 3/*#Ops*/, 6, 3, 4,
134 MVT::v16i8, 3/*#Ops*/, 1, 1, 5, // Results = #6
136 3/*#Ops*/, 6, 3, 4,
145 MVT::v16i8, 3/*#Ops*/, 1, 1, 5, // Results = #6
147 3/*#Ops*/, 6, 3, 4,
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/IR/
DDebugInfoMetadata.cpp62 SmallVector<Metadata *, 2> Ops; in getImpl() local
63 Ops.push_back(Scope); in getImpl()
65 Ops.push_back(InlinedAt); in getImpl()
66 return storeImpl(new (Ops.size()) in getImpl()
67 DILocation(Context, Storage, Line, Column, Ops), in getImpl()
261 Metadata *Ops[] = { CountNode }; in getImpl() local
262 DEFINE_GETIMPL_STORE(DISubrange, (CountNode, Lo), Ops); in getImpl()
270 Metadata *Ops[] = {Name}; in getImpl() local
271 DEFINE_GETIMPL_STORE(DIEnumerator, (Value, IsUnsigned), Ops); in getImpl()
281 Metadata *Ops[] = {nullptr, nullptr, Name}; in getImpl() local
[all …]
DMDBuilder.cpp64 SmallVector<Metadata *, 8> Ops; in createFunctionEntryCount() local
66 Ops.push_back(createString("synthetic_function_entry_count")); in createFunctionEntryCount()
68 Ops.push_back(createString("function_entry_count")); in createFunctionEntryCount()
69 Ops.push_back(createConstant(ConstantInt::get(Int64Ty, Count))); in createFunctionEntryCount()
76 Ops.push_back(createConstant(ConstantInt::get(Int64Ty, ID))); in createFunctionEntryCount()
78 return MDNode::get(Context, Ops); in createFunctionEntryCount()
104 SmallVector<Metadata *, 4> Ops; in createCallees() local
106 Ops.push_back(createConstant(F)); in createCallees()
107 return MDNode::get(Context, Ops); in createCallees()
173 SmallVector<Metadata *, 4> Ops(Fields.size() * 2 + 1); in createTBAAStructTypeNode() local
[all …]
DConstantsContext.h467 ArrayRef<Constant *> Ops;
471 ConstantExprKeyType(unsigned Opcode, ArrayRef<Constant *> Ops,
477 SubclassData(SubclassData), Ops(Ops), Indexes(Indexes),
483 SubclassData(CE->isCompare() ? CE->getPredicate() : 0), Ops(Operands),
495 Ops = Storage;
500 SubclassOptionalData == X.SubclassOptionalData && Ops == X.Ops &&
509 if (Ops.size() != CE->getNumOperands())
513 for (unsigned I = 0, E = Ops.size(); I != E; ++I)
514 if (Ops[I] != CE->getOperand(I))
523 hash_combine_range(Ops.begin(), Ops.end()),
[all …]
/external/llvm/lib/IR/
DDebugInfoMetadata.cpp59 SmallVector<Metadata *, 2> Ops; in getImpl() local
60 Ops.push_back(Scope); in getImpl()
62 Ops.push_back(InlinedAt); in getImpl()
63 return storeImpl(new (Ops.size()) in getImpl()
64 DILocation(Context, Storage, Line, Column, Ops), in getImpl()
226 Metadata *Ops[] = {Name}; in getImpl() local
227 DEFINE_GETIMPL_STORE(DIEnumerator, (Value), Ops); in getImpl()
237 Metadata *Ops[] = {nullptr, nullptr, Name}; in getImpl() local
239 Ops); in getImpl()
251 Metadata *Ops[] = {File, Scope, Name, BaseType, ExtraData}; in getImpl() local
[all …]
DConstantsContext.h444 ArrayRef<Constant *> Ops;
448 ConstantExprKeyType(unsigned Opcode, ArrayRef<Constant *> Ops,
454 SubclassData(SubclassData), Ops(Ops), Indexes(Indexes),
459 SubclassData(CE->isCompare() ? CE->getPredicate() : 0), Ops(Operands),
470 Ops = Storage;
475 SubclassOptionalData == X.SubclassOptionalData && Ops == X.Ops &&
484 if (Ops.size() != CE->getNumOperands())
488 for (unsigned I = 0, E = Ops.size(); I != E; ++I)
489 if (Ops[I] != CE->getOperand(I))
498 hash_combine_range(Ops.begin(), Ops.end()),
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DIRBuilder.cpp59 static CallInst *createCallHelper(Value *Callee, ArrayRef<Value *> Ops, in createCallHelper() argument
62 CallInst *CI = CallInst::Create(Callee, Ops, Name); in createCallHelper()
70 ArrayRef<Value *> Ops, in createInvokeHelper() argument
74 InvokeInst::Create(Invokee, NormalDest, UnwindDest, Ops, Name); in createInvokeHelper()
86 Value *Ops[] = { Ptr, Val, Size, getInt32(Align), getInt1(isVolatile) }; in CreateMemSet() local
91 CallInst *CI = createCallHelper(TheFn, Ops, this); in CreateMemSet()
113 Value *Ops[] = { Dst, Src, Size, getInt32(Align), getInt1(isVolatile) }; in CreateMemCpy() local
118 CallInst *CI = createCallHelper(TheFn, Ops, this); in CreateMemCpy()
144 Value *Ops[] = { Dst, Src, Size, getInt32(Align), getInt1(isVolatile) }; in CreateMemMove() local
149 CallInst *CI = createCallHelper(TheFn, Ops, this); in CreateMemMove()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMUnwindOpAsm.h28 SmallVector<uint8_t, 32> Ops;
39 Ops.clear(); in Reset()
64 Ops.insert(Ops.end(), Opcodes.begin(), Opcodes.end()); in EmitRaw()
74 Ops.push_back(Opcode & 0xff); in EmitInt8()
79 Ops.push_back((Opcode >> 8) & 0xff); in EmitInt16()
80 Ops.push_back(Opcode & 0xff); in EmitInt16()
85 Ops.insert(Ops.end(), Opcode, Opcode + Size); in EmitBytes()
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMUnwindOpAsm.h28 llvm::SmallVector<uint8_t, 32> Ops;
40 Ops.clear(); in Reset()
65 Ops.insert(Ops.end(), Opcodes.begin(), Opcodes.end()); in EmitRaw()
75 Ops.push_back(Opcode & 0xff); in EmitInt8()
80 Ops.push_back((Opcode >> 8) & 0xff); in EmitInt16()
81 Ops.push_back(Opcode & 0xff); in EmitInt16()
86 Ops.insert(Ops.end(), Opcode, Opcode + Size); in EmitBytes()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenDAGISel.inc79 MVT::f16, 2/*#Ops*/, 1, 7, // Results = #8
81 5/*#Ops*/, 8, 3, 4, 5, 6,
89 MVT::f16, 2/*#Ops*/, 1, 7, // Results = #8
91 5/*#Ops*/, 8, 3, 4, 5, 6,
99 MVT::f16, 2/*#Ops*/, 1, 5, // Results = #6
101 3/*#Ops*/, 6, 3, 4,
109 MVT::f16, 2/*#Ops*/, 1, 5, // Results = #6
111 3/*#Ops*/, 6, 3, 4,
132 3/*#Ops*/, 1, 4, 3,
150 MVT::f16, 2/*#Ops*/, 1, 7, // Results = #8
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenDAGISel.inc73 3/*#Ops*/, 1, 3, 4,
81 3/*#Ops*/, 1, 3, 4,
89 3/*#Ops*/, 1, 3, 4,
97 3/*#Ops*/, 1, 3, 4,
113 3/*#Ops*/, 1, 2, 3,
120 3/*#Ops*/, 1, 2, 3,
136 3/*#Ops*/, 1, 3, 4,
144 3/*#Ops*/, 1, 3, 4,
160 3/*#Ops*/, 1, 2, 3,
167 3/*#Ops*/, 1, 2, 3,
[all …]
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1527 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG, SDLoc(N)), in tryARMIndexedLoad() local
1530 MVT::i32, MVT::Other, Ops)); in tryARMIndexedLoad()
1535 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG, SDLoc(N)), in tryARMIndexedLoad() local
1538 MVT::i32, MVT::Other, Ops)); in tryARMIndexedLoad()
1585 SDValue Ops[]= { Base, Offset, getAL(CurDAG, SDLoc(N)), in tryT2IndexedLoad() local
1588 MVT::Other, Ops)); in tryT2IndexedLoad()
1602 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode() local
1603 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createGPRPairNode()
1613 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createSRegPairNode() local
1614 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createSRegPairNode()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/
DXCoreISelDAGToDAG.cpp164 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() local
167 MVT::i32, Ops)); in Select()
171 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() local
174 MVT::i32, Ops)); in Select()
178 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() local
181 MVT::i32, Ops)); in Select()
185 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() local
188 MVT::i32, Ops)); in Select()
192 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() local
195 MVT::i32, Ops)); in Select()
[all …]
/external/llvm/lib/Target/XCore/
DXCoreISelDAGToDAG.cpp164 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() local
167 MVT::i32, Ops)); in Select()
171 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() local
174 MVT::i32, Ops)); in Select()
178 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() local
181 MVT::i32, Ops)); in Select()
185 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() local
188 MVT::i32, Ops)); in Select()
192 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() local
195 MVT::i32, Ops)); in Select()
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenDAGISel.inc86 MVT::i32, 3/*#Ops*/, 0, 1, 2,
94 MVT::i32, 3/*#Ops*/, 0, 1, 2,
124 MVT::i32, 3/*#Ops*/, 0, 1, 2,
132 MVT::i32, 3/*#Ops*/, 0, 1, 2,
159 MVT::i32, 5/*#Ops*/, 0, 1, 3, 4, 5,
185 MVT::i32, 5/*#Ops*/, 0, 1, 3, 4, 5,
204 MVT::i32, 5/*#Ops*/, 0, 1, 3, 4, 5,
231 MVT::i32, 5/*#Ops*/, 0, 1, 3, 4, 5,
258 MVT::i32, 5/*#Ops*/, 0, 1, 3, 4, 5,
277 MVT::i32, 5/*#Ops*/, 0, 1, 3, 4, 5,
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/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.cpp89 SmallVector<StringRef, 5> Ops; in parseGenericRegister() local
90 if (!GenericRegPattern.match(UpperName, &Ops)) in parseGenericRegister()
95 Ops[1].getAsInteger(10, Op0); in parseGenericRegister()
96 Ops[2].getAsInteger(10, Op1); in parseGenericRegister()
97 Ops[3].getAsInteger(10, CRn); in parseGenericRegister()
98 Ops[4].getAsInteger(10, CRm); in parseGenericRegister()
99 Ops[5].getAsInteger(10, Op2); in parseGenericRegister()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.cpp118 SmallVector<StringRef, 5> Ops; in parseGenericRegister() local
119 if (!GenericRegPattern.match(UpperName, &Ops)) in parseGenericRegister()
124 Ops[1].getAsInteger(10, Op0); in parseGenericRegister()
125 Ops[2].getAsInteger(10, Op1); in parseGenericRegister()
126 Ops[3].getAsInteger(10, CRn); in parseGenericRegister()
127 Ops[4].getAsInteger(10, CRm); in parseGenericRegister()
128 Ops[5].getAsInteger(10, Op2); in parseGenericRegister()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1409 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG, SDLoc(N)), in tryARMIndexedLoad() local
1412 MVT::Other, Ops); in tryARMIndexedLoad()
1419 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG, SDLoc(N)), in tryARMIndexedLoad() local
1422 MVT::Other, Ops); in tryARMIndexedLoad()
1450 SDValue Ops[]= { Base, getAL(CurDAG, SDLoc(N)), in tryT1IndexedLoad() local
1453 MVT::i32, MVT::Other, Ops); in tryT1IndexedLoad()
1498 SDValue Ops[]= { Base, Offset, getAL(CurDAG, SDLoc(N)), in tryT2IndexedLoad() local
1501 MVT::Other, Ops); in tryT2IndexedLoad()
1517 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode() local
1518 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createGPRPairNode()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/FuzzMutate/
DOperations.h26 void describeFuzzerIntOps(std::vector<fuzzerop::OpDescriptor> &Ops);
27 void describeFuzzerFloatOps(std::vector<fuzzerop::OpDescriptor> &Ops);
28 void describeFuzzerControlFlowOps(std::vector<fuzzerop::OpDescriptor> &Ops);
29 void describeFuzzerPointerOps(std::vector<fuzzerop::OpDescriptor> &Ops);
30 void describeFuzzerAggregateOps(std::vector<fuzzerop::OpDescriptor> &Ops);
31 void describeFuzzerVectorOps(std::vector<fuzzerop::OpDescriptor> &Ops);

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