Searched refs:P5600 (Results 1 – 8 of 8) sorted by relevance
187 "MipsSubtarget::CPU::P5600",188 "The P5600 Processor", [FeatureMips32r5]>;
45 enum class CPU { P5600 }; enumerator
1 //==- MipsScheduleP5600.td - P5600 Scheduling Definitions --*- tablegen -*-===//369 // The following instruction classes are never valid on P5600.376 // The following instructions are never valid on P5600.
217 "MipsSubtarget::CPU::P5600",218 "The P5600 Processor", [FeatureMips32r5]>;
49 enum class CPU { P5600 }; enumerator
1 //==- MipsScheduleP5600.td - P5600 Scheduling Definitions --*- tablegen -*-===//572 // The following instruction classes are never valid on P5600.578 // The following instructions are never valid on P5600.
183 * Updated the P5600 scheduler model not to use instruction itineraries.
116 { "p5600", "The P5600 Processor", { Mips::ImplP5600 }, { Mips::FeatureMips32r5 } },2533 …its[Mips::ImplP5600] && ProcImpl < MipsSubtarget::CPU::P5600) ProcImpl = MipsSubtarget::CPU::P5600;