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Searched refs:PSTATE_ID_CORE_POWERDN (Results 1 – 6 of 6) sorted by relevance

/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/
Dplat_psci_handlers.c50 case PSTATE_ID_CORE_POWERDN: in tegra_soc_validate_power_state()
63 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PSTATE_ID_CORE_POWERDN; in tegra_soc_validate_power_state()
216 assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN); in tegra_soc_pwr_domain_suspend()
255 } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { in tegra_soc_pwr_domain_suspend()
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t194/
Dplat_psci_handlers.c86 case PSTATE_ID_CORE_POWERDN: in tegra_soc_validate_power_state()
146 if ((stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) { in tegra_soc_pwr_domain_suspend()
238 if (target == PSTATE_ID_CORE_POWERDN) { in tegra_get_afflvl1_pwr_state()
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/
Dplat_psci_handlers.c69 case PSTATE_ID_CORE_POWERDN: in tegra_soc_validate_power_state()
104 (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) { in tegra_soc_pwr_domain_suspend()
196 if (target == PSTATE_ID_CORE_POWERDN) { in tegra_get_afflvl1_pwr_state()
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t210/
Dtegra_def.h15 #define PSTATE_ID_CORE_POWERDN U(7) macro
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t186/
Dtegra_def.h48 #define PSTATE_ID_CORE_POWERDN U(7) macro
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t194/
Dtegra_def.h24 #define PSTATE_ID_CORE_POWERDN U(7) macro