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Searched refs:QCA956X_DDR_REG_FSM_WAIT_CTRL (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/mips/mach-ath79/qca956x/
Dddr.c223 writel(DDR_FSM_WAIT_CTRL_VAL, ddr_regs + QCA956X_DDR_REG_FSM_WAIT_CTRL); in qca956x_ddr_init()
/external/u-boot/arch/mips/mach-ath79/include/mach/
Dar71xx_regs.h296 #define QCA956X_DDR_REG_FSM_WAIT_CTRL 0xe4 macro