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Searched refs:QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/mips/mach-ath79/qca956x/
Dclk.c378 QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; in get_clocks()
/external/u-boot/arch/mips/mach-ath79/include/mach/
Dar71xx_regs.h579 #define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f macro