/external/tensorflow/tensorflow/core/platform/ |
D | cpu_info.h | 87 RDRAND = 13, enumerator
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D | cpu_info.cc | 238 case RDRAND: return cpuid->have_rdrand_; in TestFeature()
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/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/ |
D | isa.hpp | 68 bool RDRAND(void) { return CPU_Rep.f_1_ECX_[30]; } in RDRAND() function in InstructionSet
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
D | X86IntrinsicsInfo.h | 23 GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST, XGETBV, ADX, FPCLASS, FPCLASSS, enumerator 265 X86_INTRINSIC_DATA(rdrand_16, RDRAND, X86ISD::RDRAND, 0), 266 X86_INTRINSIC_DATA(rdrand_32, RDRAND, X86ISD::RDRAND, 0), 267 X86_INTRINSIC_DATA(rdrand_64, RDRAND, X86ISD::RDRAND, 0),
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D | X86ScheduleZnver1.td | 784 // RDRAND. 785 def : InstRW<[WriteMicrocoded], (instregex "RDRAND(16|32|64)r")>;
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D | X86ISelLowering.h | 549 RDRAND, enumerator
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D | X86SchedHaswell.td | 702 // RDRAND. 707 def : InstRW<[HWWriteRDRAND], (instregex "RDRAND(16|32|64)r")>;
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D | X86.td | 203 "Support RDRAND instruction">;
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D | X86SchedBroadwell.td | 1301 def: InstRW<[BWWriteResGroup112], (instregex "RDRAND(16|32|64)r")>;
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D | X86InstrInfo.td | 153 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, 2276 // RDRAND Instruction
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D | X86ISelLowering.cpp | 21600 case RDRAND: { in LowerINTRINSIC_W_CHAIN() 26100 case X86ISD::RDRAND: return "X86ISD::RDRAND"; in getTargetNodeName() 33157 if ((Op.getOpcode() != X86ISD::RDRAND && in checkBoolTestSetCCCombine()
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/external/llvm/lib/Target/X86/ |
D | X86IntrinsicsInfo.h | 24 GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST, ADX, FPCLASS, FPCLASSS, enumerator 220 X86_INTRINSIC_DATA(rdrand_16, RDRAND, X86ISD::RDRAND, 0), 221 X86_INTRINSIC_DATA(rdrand_32, RDRAND, X86ISD::RDRAND, 0), 222 X86_INTRINSIC_DATA(rdrand_64, RDRAND, X86ISD::RDRAND, 0),
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D | X86ISelLowering.h | 526 RDRAND, enumerator
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D | X86.td | 174 "Support RDRAND instruction">;
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D | X86SchedHaswell.td | 1061 // RDRAND. 1066 def : InstRW<[WriteRDRAND], (instregex "RDRAND(16|32|64)r")>;
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D | X86InstrInfo.td | 147 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, 2113 // RDRAND Instruction
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D | X86ISelLowering.cpp | 18396 case RDRAND: { in LowerINTRINSIC_W_CHAIN() 22273 case X86ISD::RDRAND: return "X86ISD::RDRAND"; in getTargetNodeName() 27103 if ((Op.getOpcode() != X86ISD::RDRAND && in checkBoolTestSetCCCombine()
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/external/boringssl/src/crypto/fipsmodule/ |
D | FIPS.md | 45 …is seeded from one of the following entropy sources in preference order: RDRAND (on Intel chips), … 49 In the case that the seed is taken from RDRAND, getrandom will also be queried with `GRND_NONBLOCK`…
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/external/XNNPACK/third_party/ |
D | cpuinfo.patch | 1196 * RDRAND instruction:
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/external/XNNPACK/cmake/ |
D | cpuinfo.patch | 1196 * RDRAND instruction:
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/external/clang/include/clang/Basic/ |
D | BuiltinsX86.def | 615 // RDRAND
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/ |
D | IntrinsicsX86.td | 2734 // RDRAND intrinsics - Return a random value and whether it is valid.
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/external/llvm/include/llvm/IR/ |
D | IntrinsicsX86.td | 4199 // RDRAND intrinsics - Return a random value and whether it is valid.
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
D | X86GenSubtargetInfo.inc | 236 { "rdrnd", "Support RDRAND instruction", { X86::FeatureRDRAND }, { } },
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