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Searched refs:REG_BASE_CRG (Results 1 – 3 of 3) sorted by relevance

/external/arm-trusted-firmware/plat/hisilicon/poplar/
Dplat_pm.c42 regval_bak = mmio_read_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP)); in poplar_pwr_domain_on()
43 mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP), 0x206); in poplar_pwr_domain_on()
44 mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP), 0x606); in poplar_pwr_domain_on()
47 regval = mmio_read_32((uintptr_t)(REG_BASE_CRG + REG_CPU_RST)); in poplar_pwr_domain_on()
49 mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_RST), regval); in poplar_pwr_domain_on()
52 regval = mmio_read_32((uintptr_t)(REG_BASE_CRG + REG_CPU_RST)); in poplar_pwr_domain_on()
54 mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_RST), regval); in poplar_pwr_domain_on()
58 mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP), regval); in poplar_pwr_domain_on()
59 mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP), regval_bak); in poplar_pwr_domain_on()
/external/u-boot/arch/arm/include/asm/arch-hi3798cv200/
Dhi3798cv200.h11 #define REG_BASE_CRG 0xF8A22000 macro
27 #define PERI_CRG46 (REG_BASE_CRG + 0xb8)
41 #define PERI_CRG47 (REG_BASE_CRG + 0xbc)
/external/arm-trusted-firmware/plat/hisilicon/poplar/include/
Dhi3798cv200.h44 #define REG_BASE_CRG (0xF8A22000) macro