| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 63 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter() local
64 RegBank.computeDerivedInfo(); in RegisterInfoEmitter()
92 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
94 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
96 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
195 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, in EmitRegUnitPressure() argument
197 unsigned NumRCs = RegBank.getRegClasses().size(); in EmitRegUnitPressure()
198 unsigned NumSets = RegBank.getNumRegPressureSets(); in EmitRegUnitPressure()
204 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure()
210 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure()
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| D | CodeGenRegisters.cpp | 76 void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) { in updateComponents() argument
85 CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]); in updateComponents()
86 CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]); in updateComponents()
100 IdxParts.push_back(RegBank.getSubRegIdx(Part)); in updateComponents()
168 void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) { in buildObjectGraph() argument
177 ExplicitSubRegIndices.push_back(RegBank.getSubRegIdx(SRIs[i])); in buildObjectGraph()
178 ExplicitSubRegs.push_back(RegBank.getReg(SRs[i])); in buildObjectGraph()
193 CodeGenRegister *Reg = RegBank.getReg(Alias); in buildObjectGraph()
255 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) { in inheritRegUnits() argument
267 CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) { in computeSubRegs() argument
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| D | CodeGenRegisters.h | 250 bool inheritRegUnits(CodeGenRegBank &RegBank);
257 unsigned getWeight(const CodeGenRegBank &RegBank) const;
389 getMatchingSubClassWithSubRegs(CodeGenRegBank &RegBank,
437 void buildRegUnitSet(const CodeGenRegBank &RegBank,
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| D | CodeGenTarget.h | 54 mutable std::unique_ptr<CodeGenRegBank> RegBank; variable
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| /external/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 77 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
79 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
81 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
190 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, in EmitRegUnitPressure() argument
192 unsigned NumRCs = RegBank.getRegClasses().size(); in EmitRegUnitPressure()
193 unsigned NumSets = RegBank.getNumRegPressureSets(); in EmitRegUnitPressure()
199 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure()
206 OS << " {" << (*Regs.begin())->getWeight(RegBank) in EmitRegUnitPressure()
207 << ", " << RegBank.getRegUnitSetWeight(RegUnits); in EmitRegUnitPressure()
218 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); in EmitRegUnitPressure()
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| D | CodeGenRegisters.cpp | 56 void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) { in updateComponents() argument
65 CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]); in updateComponents()
66 CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]); in updateComponents()
80 IdxParts.push_back(RegBank.getSubRegIdx(Parts[i])); in updateComponents()
81 RegBank.addConcatSubRegIndex(IdxParts, this); in updateComponents()
117 void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) { in buildObjectGraph() argument
126 ExplicitSubRegIndices.push_back(RegBank.getSubRegIdx(SRIs[i])); in buildObjectGraph()
127 ExplicitSubRegs.push_back(RegBank.getReg(SRs[i])); in buildObjectGraph()
142 CodeGenRegister *Reg = RegBank.getReg(Aliases[i]); in buildObjectGraph()
202 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) { in inheritRegUnits() argument
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| D | CodeGenTarget.cpp | 222 if (!RegBank) in getRegBank()
223 RegBank = llvm::make_unique<CodeGenRegBank>(Records); in getRegBank()
224 return *RegBank; in getRegBank()
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| D | CodeGenTarget.h | 70 mutable std::unique_ptr<CodeGenRegBank> RegBank; variable
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| /external/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 48 const RegisterBank &RegBank = getRegBank(Idx); in verify()
49 assert(Idx == RegBank.getID() && in verify()
51 dbgs() << "Verify " << RegBank << '\n'; in verify()
52 assert(RegBank.verify(TRI) && "RegBank is invalid"); in verify()
60 RegisterBank &RegBank = getRegBank(ID); in createRegisterBank() local
61 assert(RegBank.getID() == RegisterBank::InvalidID && in createRegisterBank()
63 RegBank.ID = ID; in createRegisterBank()
64 RegBank.Name = Name; in createRegisterBank()
195 const RegisterBank &RegBank = getRegBankFromRegClass(*RC); in getRegBankFromConstraints() local
197 assert(RegBank.covers(*RC) && in getRegBankFromConstraints()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 73 const RegisterBank &RegBank = getRegBank(Idx); in verify() local
74 assert(Idx == RegBank.getID() && in verify()
76 LLVM_DEBUG(dbgs() << "Verify " << RegBank << '\n'); in verify()
77 assert(RegBank.verify(TRI) && "RegBank is invalid"); in verify()
121 const RegisterBank &RegBank = getRegBankFromRegClass(*RC); in getRegBankFromConstraints() local
123 assert(RegBank.covers(*RC) && in getRegBankFromConstraints()
125 return &RegBank; in getRegBankFromConstraints()
234 const RegisterBank *RegBank) { in hashPartialMapping() argument
235 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0); in hashPartialMapping()
242 PartMapping.RegBank); in hash_value()
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| D | RegBankSelect.cpp | 123 const RegisterBank *DesiredRegBrank = ValMapping.BreakDown[0].RegBank; in assignmentMatch()
210 const RegisterBank *DesiredRegBrank = ValMapping.BreakDown[0].RegBank; in getRepairCost()
551 MRI->setRegBank(Reg, *ValMapping.BreakDown[0].RegBank); in applyMapping()
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| /external/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.h | 54 const RegisterBank *RegBank; member
60 const RegisterBank &RegBank) in PartialMapping()
61 : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {} in PartialMapping()
169 const RegisterBank &RegBank);
370 void recordRegBankForType(const RegisterBank &RegBank,
382 VTToRegBank.get()[SVT] = &RegBank;
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| D | RegisterBank.h | 95 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
96 RegBank.print(OS);
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.h | 59 const RegisterBank *RegBank; member
65 const RegisterBank &RegBank) in PartialMapping()
66 : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {} in PartialMapping()
461 const RegisterBank &RegBank) const;
469 const RegisterBank &RegBank) const;
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| D | RegisterBank.h | 93 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
94 RegBank.print(OS);
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 124 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass() local
125 assert(RegBank && "Can't get reg bank for virtual register"); in guessRegClass()
128 assert((RegBank->getID() == ARM::GPRRegBankID || in guessRegClass()
129 RegBank->getID() == ARM::FPRRegBankID) && in guessRegClass()
132 if (RegBank->getID() == ARM::FPRRegBankID) { in guessRegClass()
250 static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank, in selectLoadStoreOpCode() argument
254 if (RegBank == ARM::GPRRegBankID) { in selectLoadStoreOpCode()
268 if (RegBank == ARM::FPRRegBankID) { in selectLoadStoreOpCode()
896 unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID(); in select() local
904 const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize); in select()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/MIRParser/ |
| D | MIRParser.cpp | 449 Info.D.RegBank = nullptr; in parseRegisterInfo()
456 const RegisterBank *RegBank = getRegBank(MF, VReg.Class.Value); in parseRegisterInfo() local
457 if (!RegBank) in parseRegisterInfo()
463 Info.D.RegBank = RegBank; in parseRegisterInfo()
532 MRI.setRegBank(Reg, *Info.D.RegBank); in setupRegisterInfo()
865 const auto &RegBank = RBI->getRegBank(I); in initNames2RegBanks() local
867 std::make_pair(StringRef(RegBank.getName()).lower(), &RegBank)); in initNames2RegBanks()
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| D | MIParser.h | 40 const RegisterBank *RegBank; member
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| /external/llvm/lib/CodeGen/MIRParser/ |
| D | MIRParser.cpp | 380 const auto *RegBank = getRegBank(MF, VReg.Class.Value); in initializeRegisterInfo() local
381 if (!RegBank) in initializeRegisterInfo()
387 RegInfo.setRegBank(Reg, *RegBank); in initializeRegisterInfo()
736 const auto &RegBank = RBI->getRegBank(I); in initNames2RegBanks() local
738 std::make_pair(StringRef(RegBank.getName()).lower(), &RegBank)); in initNames2RegBanks()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenRegisterBank.inc | 70 // Assert that RegBank indices match their ID's
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUGenRegisterBankInfo.def | 38 // StartIdx, Length, RegBank
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenRegisterBank.inc | 91 // Assert that RegBank indices match their ID's
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86GenRegisterBankInfo.def | 16 /* StartIdx, Length, RegBank */
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| D | X86InstructionSelector.cpp | 199 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass() local
200 return getRegClass(Ty, RegBank); in getRegClass()
1260 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectMergeValues() local
1264 MRI.setRegBank(DefReg, RegBank); in selectMergeValues()
1270 MRI.setRegBank(Tmp, RegBank); in selectMergeValues()
1329 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in materializeFP() local
1333 unsigned Opc = getLoadStoreOp(DstTy, RegBank, TargetOpcode::G_LOAD, Align); in materializeFP()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenRegisterBank.inc | 124 // Assert that RegBank indices match their ID's
|