| /external/llvm/test/CodeGen/X86/ |
| D | win64_frame.ll | 2 ; RUN: llc < %s -mtriple=x86_64-pc-win32 -mattr=+sahf | FileCheck %s --check-prefix=SAHF
160 ; SAHF: lock cmpxchgq
161 ; SAHF-NEXT: seto %al
162 ; SAHF-NEXT: lahf
171 ; SAHF: callq dummy
172 ; SAHF-NEXT: pushq
173 ; SAHF: addb $127, %al
174 ; SAHF-NEXT: sahf
175 ; SAHF-NEXT: popq
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| D | eflags-copy-expansion.mir | 57 ; CHECK-NEXT: SAHF implicit-def %eflags, implicit %ah
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| /external/v8/src/codegen/ |
| D | cpu-features.h | 21 SAHF, enumerator
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | cmpxchg-clobber-flags.ll | 7 …u -verify-machineinstrs -mattr=+sahf %s -o - | FileCheck %s --check-prefixes=64-ALL,64-GOOD-RA-SAHF
8 …strs -mattr=+sahf -pre-RA-sched=fast %s -o - | FileCheck %s --check-prefixes=64-ALL,64-FAST-RA-SAHF
9 …u -verify-machineinstrs -mcpu=corei7 %s -o - | FileCheck %s --check-prefixes=64-ALL,64-GOOD-RA-SAHF
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| D | win64_frame.ll | 3 …lc < %s -mtriple=x86_64-pc-win32 -mattr=+sahf | FileCheck %s --check-prefix=ALL --check-prefix=SAHF
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| D | flags-copy-lowering.mir | 3 # Lower various interesting copy patterns of EFLAGS without using LAHF/SAHF.
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 523 SAHF, enumerator
|
| D | X86.td | 200 "Support LAHF and SAHF instructions">;
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| D | X86SchedHaswell.td | 502 // LAHF SAHF.
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| D | X86InstrInfo.td | 145 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
1584 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
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| D | X86InstrInfo.cpp | 4581 BuildMI(MBB, MI, DL, get(X86::SAHF)); in copyPhysReg()
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| D | X86ISelLowering.cpp | 14913 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl); in ConvertCmpIfNecessary()
15679 Opc == X86ISD::SAHF) in isX86LogicalCmp()
22272 case X86ISD::SAHF: return "X86ISD::SAHF"; in getTargetNodeName()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 546 SAHF, enumerator
|
| D | X86.td | 226 "Support LAHF and SAHF instructions">;
|
| D | X86InstrInfo.td | 151 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
1741 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
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| D | X86ISelLowering.cpp | 18013 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl); in ConvertCmpIfNecessary()
18788 Opc == X86ISD::SAHF) in isX86LogicalCmp()
26099 case X86ISD::SAHF: return "X86ISD::SAHF"; in getTargetNodeName()
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| /external/v8/src/codegen/x64/ |
| D | assembler-x64.cc | 89 if (cpu.has_sahf() && FLAG_enable_sahf) supported_ |= 1u << SAHF; in ProbeImpl()
118 CpuFeatures::IsSupported(SAHF), CpuFeatures::IsSupported(AVX), in PrintFeatures()
2632 DCHECK(IsEnabled(SAHF)); in sahf()
|
| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 600 #define SAHF CHOICE(sahf, sahf, sahf) macro
1313 #define SAHF sahf macro
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| /external/v8/src/compiler/backend/x64/ |
| D | code-generator-x64.cc | 1533 if (CpuFeatures::IsSupported(SAHF)) { in AssembleArchInstruction()
1534 CpuFeatureScope sahf_scope(tasm(), SAHF); in AssembleArchInstruction()
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| /external/capstone/arch/X86/ |
| D | X86GenAsmWriter1_reduce.inc | 1224 2914U, // SAHF
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| D | X86GenAsmWriter_reduce.inc | 1224 4838U, // SAHF
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| D | X86GenAsmWriter1.inc | 2474 11540U, // SAHF
8745 0U, // SAHF
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| D | X86GenAsmWriter.inc | 2474 14414U, // SAHF
8745 0U, // SAHF
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| /external/llvm/docs/ |
| D | CodeGenerator.rst | 403 MI = BuildMI(MBB, DL, TII.get(X86::SAHF));
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| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | CodeGenerator.rst | 403 MI = BuildMI(MBB, DL, TII.get(X86::SAHF));
|