Searched refs:SDCR (Results 1 – 6 of 6) sorted by relevance
95 ldcopr r5, SDCR154 ldcopr r1, SDCR
122 stcopr r0, SDCR
485 #define SDCR p15, 0, c1, c3, 1 macro
54 macro. Here the affected bits are ``SDCR.SPD``, which should also be assigned to
373 For ARMv8.5 the counter gets disabled by setting ``SDCR.SCCD`` bit on1713 - Debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR are initialised to avoid
289 - ``SDCR``. The ``SDCR.SPD`` field is set to disable AArch32 Secure