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Searched refs:SDIV (Results 1 – 25 of 138) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/GlobalISel/
Dx86_64-legalize-sdiv.mir50 ; CHECK: [[SDIV:%[0-9]+]]:_(s8) = G_SDIV [[TRUNC]], [[TRUNC1]]
51 ; CHECK: $al = COPY [[SDIV]](s8)
82 ; CHECK: [[SDIV:%[0-9]+]]:_(s16) = G_SDIV [[TRUNC]], [[TRUNC1]]
83 ; CHECK: $ax = COPY [[SDIV]](s16)
110 ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[COPY]], [[COPY1]]
111 ; CHECK: $eax = COPY [[SDIV]](s32)
136 ; CHECK: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[COPY]], [[COPY1]]
137 ; CHECK: $rax = COPY [[SDIV]](s64)
Dx86-legalize-sdiv.mir45 ; CHECK: [[SDIV:%[0-9]+]]:_(s8) = G_SDIV [[TRUNC]], [[TRUNC1]]
46 ; CHECK: $al = COPY [[SDIV]](s8)
77 ; CHECK: [[SDIV:%[0-9]+]]:_(s16) = G_SDIV [[TRUNC]], [[TRUNC1]]
78 ; CHECK: $ax = COPY [[SDIV]](s16)
105 ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[COPY]], [[COPY1]]
106 ; CHECK: $eax = COPY [[SDIV]](s32)
Dx86_64-irtranslator.ll141 ; CHECK: [[SDIV:%[0-9]+]]:_(s8) = G_SDIV [[TRUNC]], [[TRUNC1]]
142 ; CHECK: $al = COPY [[SDIV]](s8)
156 ; CHECK: [[SDIV:%[0-9]+]]:_(s16) = G_SDIV [[TRUNC]], [[TRUNC1]]
157 ; CHECK: $ax = COPY [[SDIV]](s16)
169 ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[COPY]], [[COPY1]]
170 ; CHECK: $eax = COPY [[SDIV]](s32)
182 ; CHECK: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[COPY]], [[COPY1]]
183 ; CHECK: $rax = COPY [[SDIV]](s64)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dcortex-a57-misched-basic.ll6 ; SDIV should be scheduled at the block's begin (20 cyc of independent M unit).
17 ; GENERIC: SDIV
22 ; A57_SCHED: SDIV
35 ; GENERIC: SDIV
36 ; A57_SCHED: SDIV
Dcortexr52-misched-basic.ll17 ; CHECK: SDIV
22 ; GENERIC: SDIV
23 ; R52_SCHED: SDIV
/external/u-boot/board/samsung/smdkc100/
Dlowlevel_init.S91 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
94 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
97 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/
Dlegalize-rem.mir66 ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[TRUNC]], [[TRUNC1]]
67 ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SDIV]], [[TRUNC1]]
102 ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
103 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
Dlegalize-div.mir36 ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
37 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp426 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
430 { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
434 { ISD::SDIV, MVT::v4i16, ReciprocalDivCost}, in getArithmeticInstrCost()
438 { ISD::SDIV, MVT::v8i8, ReciprocalDivCost}, in getArithmeticInstrCost()
443 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
447 { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
451 { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
455 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp471 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
475 { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
479 { ISD::SDIV, MVT::v4i16, ReciprocalDivCost}, in getArithmeticInstrCost()
483 { ISD::SDIV, MVT::v8i8, ReciprocalDivCost}, in getArithmeticInstrCost()
488 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
492 { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
496 { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
500 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
/external/u-boot/board/samsung/goni/
Dlowlevel_init.S257 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
260 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
263 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
266 ldr r1, =0x80600603 @ SDIV 3, PDIV 6, MDIV 96
/external/u-boot/board/samsung/odroid/
Dodroid.c128 clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1); in board_clock_init()
129 set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1); in board_clock_init()
212 set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1); in board_clock_init()
Dsetup.h11 #define SDIV(x) ((x) & 0x7) macro
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp98 if (ISD == ISD::SDIV && in getArithmeticInstrCost()
121 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
123 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
224 { ISD::SDIV, MVT::v32i8, 32*20 }, in getArithmeticInstrCost()
225 { ISD::SDIV, MVT::v16i16, 16*20 }, in getArithmeticInstrCost()
226 { ISD::SDIV, MVT::v8i32, 8*20 }, in getArithmeticInstrCost()
227 { ISD::SDIV, MVT::v4i64, 4*20 }, in getArithmeticInstrCost()
273 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence in getArithmeticInstrCost()
275 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence in getArithmeticInstrCost()
282 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) in getArithmeticInstrCost()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp341 case ISD::SDIV: in Select()
352 if (N->getOpcode() == ISD::SDIV) { in Select()
364 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; in Select()
/external/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp339 case ISD::SDIV: in Select()
350 if (N->getOpcode() == ISD::SDIV) { in Select()
362 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; in Select()
DLeonFeatures.td39 "AT697E erratum fix: Do not emit SDIV, emit SDIVCC instead">;
/external/llvm/lib/Target/Lanai/
DLanaiTargetTransformInfo.h71 case ISD::SDIV:
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiTargetTransformInfo.h93 case ISD::SDIV:
/external/llvm/lib/Target/BPF/
DBPFISelDAGToDAG.cpp133 case ISD::SDIV: { in Select()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp247 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || in getArithmeticInstrCost()
252 if (ISD == ISD::SDIV || ISD == ISD::SREM) { in getArithmeticInstrCost()
294 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
312 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
332 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
336 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
358 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. in getArithmeticInstrCost()
360 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence in getArithmeticInstrCost()
366 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. in getArithmeticInstrCost()
368 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence in getArithmeticInstrCost()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h201 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
/external/vixl/test/aarch32/config/
Dcond-rd-rn-rm-a32.json43 "Sdiv", // SDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
Dcond-rd-rn-rm-t32.json42 "Sdiv", // SDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1

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