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Searched refs:SDRAM_CFG_REG (Results 1 – 5 of 5) sorted by relevance

/external/u-boot/drivers/ram/
Dbmips_ram.c16 #define SDRAM_CFG_REG 0x0 macro
54 val = readl_be(priv->regs + SDRAM_CFG_REG); in bcm6318_get_ram_size()
80 val = readl_be(priv->regs + SDRAM_CFG_REG); in bcm6338_get_ram_size()
/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_training.c400 SDRAM_CFG_REG, data_value, in hws_ddr3_tip_init_controller()
411 SDRAM_CFG_REG, in hws_ddr3_tip_init_controller()
416 SDRAM_CFG_REG, in hws_ddr3_tip_init_controller()
865 SDRAM_CFG_REG, 0x40000, 0x40000)); in ddr3_pre_algo_config()
1133 (dev_num, access_type, if_id, SDRAM_CFG_REG, in adll_calibration()
1137 (dev_num, access_type, if_id, SDRAM_CFG_REG, in adll_calibration()
1186 (dev_num, access_type, if_id, SDRAM_CFG_REG, in adll_calibration()
1190 (dev_num, access_type, if_id, SDRAM_CFG_REG, in adll_calibration()
1421 SDRAM_CFG_REG, 0, 0x10000000)); in ddr3_tip_freq_set()
1425 SDRAM_CFG_REG, 0x10000000, 0x10000000)); in ddr3_tip_freq_set()
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Dddr3_training_leveling.c157 SDRAM_CFG_REG, 0, (1 << 30))); in ddr3_tip_dynamic_read_leveling()
161 SDRAM_CFG_REG, (1 << 30), (1 << 30))); in ddr3_tip_dynamic_read_leveling()
529 SDRAM_CFG_REG, 0, (1 << 30))); in ddr3_tip_dynamic_per_bit_read_leveling()
533 SDRAM_CFG_REG, (1 << 30), (1 << 30))); in ddr3_tip_dynamic_per_bit_read_leveling()
1767 ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, if_id, SDRAM_CFG_REG, in mv_ddr_rl_dqs_burst()
1772 ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, if_id, SDRAM_CFG_REG, in mv_ddr_rl_dqs_burst()
1955 ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, if_id, SDRAM_CFG_REG, in mv_ddr_rl_dqs_burst()
1960 ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, if_id, SDRAM_CFG_REG, in mv_ddr_rl_dqs_burst()
Dmv_ddr_regs.h36 #define SDRAM_CFG_REG 0x1400 macro
Dmv_ddr_plat.c928 SDRAM_CFG_REG, 0x0, 0x8000)); in ddr3_silicon_post_init()
947 bus_width = (reg_read(SDRAM_CFG_REG) & 0x8000) >> in ddr3_get_bus_width()