/external/arm-trusted-firmware/services/spd/tspd/ |
D | tspd_main.c | 64 assert(handle == cm_get_context(SECURE)); in tspd_handle_sp_preemption() 65 cm_el1_sysregs_context_save(SECURE); in tspd_handle_sp_preemption() 116 assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE)); in tspd_sel1_interrupt_handler() 139 cm_el1_sysregs_context_restore(SECURE); in tspd_sel1_interrupt_handler() 140 cm_set_elr_spsr_el3(SECURE, (uint64_t) &tsp_vectors->sel1_intr_entry, in tspd_sel1_interrupt_handler() 143 cm_set_next_eret_context(SECURE); in tspd_sel1_interrupt_handler() 167 assert(get_interrupt_src_ss(flags) == SECURE); in tspd_ns_interrupt_handler() 173 disable_intr_rm_local(INTR_TYPE_NS, SECURE); in tspd_ns_interrupt_handler() 196 tsp_ep_info = bl31_plat_get_next_image_ep_info(SECURE); in tspd_setup() 223 bl31_set_next_image_type(SECURE); in tspd_setup() [all …]
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D | tspd_common.c | 48 cm_set_context(&tsp_ctx->cpu_ctx, SECURE); in tspd_init_tsp_ep_state() 51 ep_attr = SECURE | EP_ST_ENABLE; in tspd_init_tsp_ep_state() 79 assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); in tspd_synchronous_sp_entry() 80 cm_el1_sysregs_context_restore(SECURE); in tspd_synchronous_sp_entry() 81 cm_set_next_eret_context(SECURE); in tspd_synchronous_sp_entry() 104 assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); in tspd_synchronous_sp_exit() 105 cm_el1_sysregs_context_save(SECURE); in tspd_synchronous_sp_exit() 131 cm_set_elr_el3(SECURE, in tspd_abort_preempted_smc()
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D | tspd_pm.c | 46 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_off_entry); in tspd_cpu_off_handler() 85 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_suspend_entry); in tspd_cpu_suspend_handler() 128 disable_intr_rm_local(INTR_TYPE_NS, SECURE); in tspd_cpu_on_finish_handler() 163 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_resume_entry); in tspd_cpu_suspend_finish_handler() 205 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_off_entry); in tspd_system_off() 231 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_reset_entry); in tspd_system_reset()
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/external/arm-trusted-firmware/services/spd/tlkd/ |
D | tlkd_common.c | 28 cm_el1_sysregs_context_save(SECURE); in tlkd_va_translate() 65 cm_el1_sysregs_context_restore(SECURE); in tlkd_va_translate() 68 write_scr(cm_get_scr_el3(SECURE)); in tlkd_va_translate() 95 cm_set_context(&tlk_ctx->cpu_ctx, SECURE); in tlkd_init_tlk_ep_state() 106 ep_attr = SECURE | EP_ST_ENABLE; in tlkd_init_tlk_ep_state() 131 assert(cm_get_context(SECURE) == &tlk_ctx->cpu_ctx); in tlkd_synchronous_sp_entry() 132 cm_el1_sysregs_context_restore(SECURE); in tlkd_synchronous_sp_entry() 133 cm_set_next_eret_context(SECURE); in tlkd_synchronous_sp_entry() 157 assert(cm_get_context(SECURE) == &tlk_ctx->cpu_ctx); in tlkd_synchronous_sp_exit() 158 cm_el1_sysregs_context_save(SECURE); in tlkd_synchronous_sp_exit()
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D | tlkd_main.c | 64 tlk_ep_info = bl31_plat_get_next_image_ep_info(SECURE); in tlkd_setup() 113 tlk_entry_point = bl31_plat_get_next_image_ep_info(SECURE); in tlkd_init() 173 assert(handle == cm_get_context(SECURE)); in tlkd_smc_handler() 174 cm_el1_sysregs_context_save(SECURE); in tlkd_smc_handler() 245 assert(&tlk_ctx.cpu_ctx == cm_get_context(SECURE)); in tlkd_smc_handler() 256 cm_el1_sysregs_context_restore(SECURE); in tlkd_smc_handler() 257 cm_set_next_eret_context(SECURE); in tlkd_smc_handler() 328 cm_el1_sysregs_context_save(SECURE); in tlkd_smc_handler()
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/external/arm-trusted-firmware/services/spd/opteed/ |
D | opteed_main.c | 73 assert(&optee_ctx->cpu_ctx == cm_get_context(SECURE)); in opteed_sel1_interrupt_handler() 75 cm_set_elr_el3(SECURE, (uint64_t)&optee_vector_table->fiq_entry); in opteed_sel1_interrupt_handler() 76 cm_el1_sysregs_context_restore(SECURE); in opteed_sel1_interrupt_handler() 77 cm_set_next_eret_context(SECURE); in opteed_sel1_interrupt_handler() 109 optee_ep_info = bl31_plat_get_next_image_ep_info(SECURE); in opteed_setup() 167 optee_entry_point = bl31_plat_get_next_image_ep_info(SECURE); in opteed_init() 232 assert(&optee_ctx->cpu_ctx == cm_get_context(SECURE)); in opteed_smc_handler() 239 cm_set_elr_el3(SECURE, (uint64_t) in opteed_smc_handler() 242 cm_set_elr_el3(SECURE, (uint64_t) in opteed_smc_handler() 246 cm_el1_sysregs_context_restore(SECURE); in opteed_smc_handler() [all …]
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D | opteed_common.c | 39 cm_set_context(&optee_ctx->cpu_ctx, SECURE); in opteed_init_optee_ep_state() 42 ep_attr = SECURE | EP_ST_ENABLE; in opteed_init_optee_ep_state() 78 assert(cm_get_context(SECURE) == &optee_ctx->cpu_ctx); in opteed_synchronous_sp_entry() 79 cm_el1_sysregs_context_restore(SECURE); in opteed_synchronous_sp_entry() 80 cm_set_next_eret_context(SECURE); in opteed_synchronous_sp_entry() 103 assert(cm_get_context(SECURE) == &optee_ctx->cpu_ctx); in opteed_synchronous_sp_exit() 104 cm_el1_sysregs_context_save(SECURE); in opteed_synchronous_sp_exit()
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D | opteed_pm.c | 39 cm_set_elr_el3(SECURE, (uint64_t) &optee_vector_table->cpu_off_entry); in opteed_cpu_off_handler() 75 cm_set_elr_el3(SECURE, (uint64_t) &optee_vector_table->cpu_suspend_entry); in opteed_cpu_suspend_handler() 144 cm_set_elr_el3(SECURE, (uint64_t) &optee_vector_table->cpu_resume_entry); in opteed_cpu_suspend_finish_handler() 180 cm_set_elr_el3(SECURE, (uint64_t) &optee_vector_table->system_off_entry); in opteed_system_off() 200 cm_set_elr_el3(SECURE, (uint64_t) &optee_vector_table->system_reset_entry); in opteed_system_reset()
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/external/arm-trusted-firmware/plat/arm/common/aarch64/ |
D | arm_bl2_mem_params_desc.c | 28 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), 46 SECURE | EXECUTABLE | EP_FIRST_EXE), 66 SECURE | EXECUTABLE | EP_FIRST_EXE), 98 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), 109 VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), 128 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), 146 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), 161 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
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/external/arm-trusted-firmware/bl1/ |
D | bl1_fwu.c | 240 if (GET_SECURITY_STATE(flags) == SECURE) { in bl1_fwu_image_copy() 376 if (GET_SECURITY_STATE(flags) == SECURE) { in bl1_fwu_image_auth() 383 if (GET_SECURITY_STATE(image_desc->ep_info.h.attr) == SECURE) { in bl1_fwu_image_auth() 513 (GET_SECURITY_STATE(flags) == SECURE) || in bl1_fwu_image_execute() 535 *handle = cm_get_context(SECURE); in bl1_fwu_image_execute() 537 *handle = smc_get_ctx(SECURE); in bl1_fwu_image_execute() 567 assert(GET_SECURITY_STATE(image_desc->ep_info.h.attr) == SECURE); in bl1_fwu_image_resume() 570 if (caller_sec_state == SECURE) { in bl1_fwu_image_resume() 581 resume_sec_state = SECURE; in bl1_fwu_image_resume() 585 (resume_sec_state == SECURE) ? "secure" : "normal"); in bl1_fwu_image_resume() [all …]
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/external/arm-trusted-firmware/plat/qemu/common/ |
D | qemu_bl2_mem_params_desc.c | 27 SECURE | EXECUTABLE | EP_FIRST_EXE), 44 SECURE | EXECUTABLE | EP_FIRST_EXE), 66 #define BL32_EP_ATTRIBS (SECURE | EXECUTABLE) 69 #define BL32_EP_ATTRIBS (SECURE | EXECUTABLE | EP_FIRST_EXE) 97 entry_point_info_t, SECURE | NON_EXECUTABLE), 115 entry_point_info_t, SECURE | NON_EXECUTABLE),
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/external/arm-trusted-firmware/plat/hisilicon/poplar/ |
D | bl2_plat_mem_params_desc.c | 28 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), 46 SECURE | EXECUTABLE | EP_FIRST_EXE), 66 SECURE | EXECUTABLE | EP_FIRST_EXE), 92 VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), 111 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), 129 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
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/external/arm-trusted-firmware/plat/hisilicon/hikey960/ |
D | hikey960_bl2_mem_params_desc.c | 28 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), 46 SECURE | EXECUTABLE | EP_FIRST_EXE), 66 SECURE | EXECUTABLE | EP_FIRST_EXE), 92 VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), 111 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), 129 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
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/external/arm-trusted-firmware/plat/hisilicon/hikey/ |
D | hikey_bl2_mem_params_desc.c | 28 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), 46 SECURE | EXECUTABLE | EP_FIRST_EXE), 66 SECURE | EXECUTABLE | EP_FIRST_EXE), 92 VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), 111 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), 129 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
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/external/arm-trusted-firmware/services/std_svc/spm_mm/ |
D | spm_mm_main.c | 95 cm_set_context(&(ctx->cpu_ctx), SECURE); in spm_sp_synchronous_entry() 98 cm_el1_sysregs_context_restore(SECURE); in spm_sp_synchronous_entry() 99 cm_set_next_eret_context(SECURE); in spm_sp_synchronous_entry() 109 cm_el1_sysregs_context_save(SECURE); in spm_sp_synchronous_entry() 290 assert(handle == cm_get_context(SECURE)); in spm_mm_smc_handler() 293 cm_set_elr_spsr_el3(SECURE, read_elr_el1(), read_spsr_el1()); in spm_mm_smc_handler()
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/external/arm-trusted-firmware/services/spd/trusty/ |
D | trusty.c | 231 entry_point_info_t *ep_info = bl31_plat_get_next_image_ep_info(SECURE); in trusty_smc_handler() 248 ret = trusty_context_switch(SECURE, x1, 0, 0, 0); in trusty_smc_handler() 299 ep_info = bl31_plat_get_next_image_ep_info(SECURE); in trusty_init() 305 cm_set_context(&ctx->cpu_ctx, SECURE); in trusty_init() 315 cm_set_elr_el3(SECURE, ep_info->pc + (1U << 5)); in trusty_init() 318 cm_el1_sysregs_context_restore(SECURE); in trusty_init() 319 fpregs_context_restore(get_fpregs_ctx(cm_get_context(SECURE))); in trusty_init() 320 cm_set_next_eret_context(SECURE); in trusty_init() 410 ep_info = bl31_plat_get_next_image_ep_info(SECURE); in trusty_setup() 439 SET_PARAM_HEAD(ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE); in trusty_setup()
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/external/arm-trusted-firmware/plat/marvell/common/aarch64/ |
D | marvell_bl2_mem_params_desc.c | 29 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), 47 SECURE | EXECUTABLE | EP_FIRST_EXE), 67 SECURE | EXECUTABLE | EP_FIRST_EXE), 93 VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
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/external/arm-trusted-firmware/plat/rpi/rpi3/aarch64/ |
D | rpi3_bl2_mem_params_desc.c | 29 SECURE | EXECUTABLE | EP_FIRST_EXE), 56 SECURE | EXECUTABLE), 77 SECURE | NON_EXECUTABLE), 98 SECURE | NON_EXECUTABLE),
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/external/arm-trusted-firmware/bl1/tbbr/ |
D | tbbr_img_desc.c | 21 VERSION_1, entry_point_info_t, SECURE), 39 VERSION_1, entry_point_info_t, SECURE), 50 VERSION_1, entry_point_info_t, SECURE | EXECUTABLE),
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/external/arm-trusted-firmware/plat/imx/imx7/common/ |
D | imx7_bl2_mem_params_desc.c | 19 SECURE | EXECUTABLE | EP_FIRST_EXE), 35 SECURE | NON_EXECUTABLE), 50 SECURE | NON_EXECUTABLE),
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/external/arm-trusted-firmware/plat/intel/soc/common/ |
D | bl2_plat_mem_params_desc.c | 28 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), 46 SECURE | EXECUTABLE | EP_FIRST_EXE), 66 SECURE | EXECUTABLE | EP_FIRST_EXE),
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/external/arm-trusted-firmware/plat/layerscape/common/aarch64/ |
D | ls_bl2_mem_params_desc.c | 32 SECURE | EXECUTABLE | EP_FIRST_EXE), 53 SECURE | EXECUTABLE | EP_FIRST_EXE), 78 VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
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/external/arm-trusted-firmware/include/common/ |
D | ep_info.h | 19 #define SECURE EP_SECURE macro 21 #define sec_state_is_valid(s) (((s) == SECURE) || ((s) == NON_SECURE))
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/external/arm-trusted-firmware/plat/arm/common/aarch32/ |
D | arm_bl2_mem_params_desc.c | 28 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), 45 SECURE | EXECUTABLE | EP_FIRST_EXE),
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/external/arm-trusted-firmware/lib/el3_runtime/aarch64/ |
D | context_mgmt.c | 96 if (security_state != SECURE) in cm_setup_context() 185 if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) { in cm_setup_context() 550 if (security_state == SECURE) in cm_el1_sysregs_context_save() 567 if (security_state == SECURE) in cm_el1_sysregs_context_restore()
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