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Searched refs:SMRD (Results 1 – 25 of 29) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dsmrd.ll8 ; SMRD load with an immediate offset.
20 ; SMRD load with the largest possible immediate offset.
32 ; SMRD load with an offset greater than the largest possible immediate.
47 ; SMRD load with a 64-bit offset
62 ; SMRD load with the largest possible immediate offset on VI
76 ; SMRD load with an offset greater than the largest possible immediate on VI
/external/llvm/test/CodeGen/AMDGPU/
Dsmrd.ll5 ; SMRD load with an immediate offset.
17 ; SMRD load with the largest possible immediate offset.
29 ; SMRD load with an offset greater than the largest possible immediate.
44 ; SMRD load with a 64-bit offset
59 ; SMRD load with the largest possible immediate offset on VI
73 ; SMRD load with an offset greater than the largest possible immediate on VI
87 ; SMRD load using the load.const intrinsic with an immediate offset
100 ; SMRD load using the load.const intrinsic with the largest possible immediate
113 ; SMRD load using the load.const intrinsic with an offset greater than the
130 ; SMRD load with the largest possible immediate offset on VI
[all …]
Dsalu-to-valu.ll53 ; Test moving an SMRD instruction to the VALU
90 ; Test moving an SMRD with an immediate offset to the VALU
106 ; Use a big offset that will use the SMRD literal offset on CI
/external/llvm/lib/Target/AMDGPU/
DGCNHazardRecognizer.cpp197 int GCNHazardRecognizer::checkSMRDHazards(MachineInstr *SMRD) { in checkSMRDHazards() argument
202 WaitStatesNeeded = checkSMEMSoftClauseHazards(SMRD); in checkSMRDHazards()
213 for (const MachineOperand &Use : SMRD->uses()) { in checkSMRDHazards()
DGCNHazardRecognizer.h43 int checkSMRDHazards(MachineInstr *SMRD);
DSIInstrInfo.h296 return MI.getDesc().TSFlags & SIInstrFlags::SMRD; in isSMRD()
300 return get(Opcode).TSFlags & SIInstrFlags::SMRD; in isSMRD()
360 return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD); in isScalarUnit()
DSIInstrFormats.td40 field bits<1> SMRD = 0;
76 let TSFlags{18} = SMRD;
345 class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
349 let SMRD = 1;
DSIDefines.h37 SMRD = 1 << 18, enumerator
DCIInstructions.td93 // SMRD Instructions
DSIInstructions.td41 // SMRD Instructions
45 // SMRD instructions, because the SReg_32_XM0 register class does not include M0
46 // and writing to M0 from an SMRD instruction will hang the GPU.
2361 // SMRD Patterns
2369 (vt (!cast<SMRD>(Instr#"_IMM") $sbase, $offset))
2375 (vt (!cast<SMRD>(Instr#"_SGPR") $sbase, $offset))
2380 (vt (!cast<SMRD>(Instr#"_IMM_ci") $sbase, $offset))
2386 // Global and constant loads can be selected to either MUBUF or SMRD
2387 // instructions, but SMRD instructions are faster so we want the instruction
DSIRegisterInfo.td256 // Subset of SReg_32 without M0 for SMRD instructions and alike.
DSIInstrInfo.td77 // Specify an SMRD opcode for SI and SMEM opcode for VI
986 // SMRD classes
990 SMRD <outs, ins, "", pattern>,
998 SMRD <outs, ins, asm, []>,
1008 SMRD <outs, ins, asm, []>,
1019 SMRD <outs, ins, asm, pattern>,
1029 SMRD <outs, ins, asm, pattern>,
1119 def _IMM_ci : SMRD <
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUInstructionSelector.cpp537 MachineInstr *SMRD = BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg) in selectSMRD() local
541 return constrainSelectedInstRegOperands(*SMRD, TII, TRI, RBI); in selectSMRD()
547 MachineInstr *SMRD = BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg) in selectSMRD() local
551 return constrainSelectedInstRegOperands(*SMRD, TII, TRI, RBI); in selectSMRD()
560 MachineInstr *SMRD = BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg) in selectSMRD() local
564 return constrainSelectedInstRegOperands(*SMRD, TII, TRI, RBI); in selectSMRD()
570 MachineInstr *SMRD = BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg) in selectSMRD() local
574 return constrainSelectedInstRegOperands(*SMRD, TII, TRI, RBI); in selectSMRD()
DSMInstructions.td31 let SMRD = 1;
236 // SMRD instructions, because the SReg_32_XM0 register class does not include M0
237 // and writing to M0 from an SMRD instruction will hang the GPU.
240 // does sdst for SMRD on SI/CI?
251 // FIXME: exec_lo/exec_hi appear to be allowed for SMRD loads on
419 // Global and constant loads can be selected to either MUBUF or SMRD
420 // instructions, but SMRD instructions are faster so we want the instruction
478 // FIXME: Assembler should reject trying to use glc on SMRD
715 let SMRD = ps.SMRD;
DGCNHazardRecognizer.cpp358 int GCNHazardRecognizer::checkSMRDHazards(MachineInstr *SMRD) { in checkSMRDHazards() argument
362 WaitStatesNeeded = checkSoftClauseHazards(SMRD); in checkSMRDHazards()
374 bool IsBufferSMRD = TII.isBufferSMRD(*SMRD); in checkSMRDHazards()
376 for (const MachineOperand &Use : SMRD->uses()) { in checkSMRDHazards()
DGCNHazardRecognizer.h64 int checkSMRDHazards(MachineInstr *SMRD);
DSIInstrInfo.h421 return MI.getDesc().TSFlags & SIInstrFlags::SMRD; in isSMRD()
425 return get(Opcode).TSFlags & SIInstrFlags::SMRD; in isSMRD()
535 return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD); in isScalarUnit()
DSIInstrFormats.td51 field bit SMRD = 0;
146 let TSFlags{18} = SMRD;
DSIDefines.h48 SMRD = 1 << 18, enumerator
DSIRegisterInfo.td413 // Subset of SReg_32 without M0 for SMRD instructions and alike.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dsmrd.ll6 ; SMRD load with an immediate offset.
18 ; SMRD load with the largest possible immediate offset.
30 ; SMRD load with an offset greater than the largest possible immediate.
45 ; SMRD load with a 64-bit offset
60 ; SMRD load with the largest possible immediate offset on VI
74 ; SMRD load with an offset greater than the largest possible immediate on VI
105 ; SMRD load using the load.const.v4i32 intrinsic with an immediate offset
118 ; SMRD load using the load.const.v4i32 intrinsic with the largest possible immediate
132 ; SMRD load using the load.const.v4i32 intrinsic with an offset greater than the
149 ; SMRD load with the largest possible immediate offset on VI
[all …]
Dsalu-to-valu.ll53 ; Test moving an SMRD instruction to the VALU
90 ; Test moving an SMRD with an immediate offset to the VALU
106 ; Use a big offset that will use the SMRD literal offset on CI
/external/llvm/docs/
DAMDGPUUsage.rst59 SMRD Instructions
61 Only the s_load_dword* SMRD instructions are supported.
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DAMDGPUOperandSyntax.rst538 SMRD/SMEM Modifiers
DAMDGPUAsmGFX7.rst345 SMRD chapter

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