Home
last modified time | relevance | path

Searched refs:SOPC (Results 1 – 18 of 18) sorted by relevance

/external/llvm/docs/
DAMDGPUUsage.rst71 SOPC Instructions
73 All SOPC instructions are supported.
/external/mesa3d/src/amd/compiler/
Daco_opcodes.py39 SOPC = 5 variable in Format
469 SOPC = { variable
492 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOPC:
493 opcode(name, gfx7, gfx9, gfx10, Format.SOPC)
Daco_ir.h76 SOPC = 5, enumerator
930 format == Format::SOPC || in isSALU()
Daco_assembler.cpp151 case Format::SOPC: { in emit_instruction()
Daco_validate.cpp239 instr->format == Format::SOPC || in validate_ir()
/external/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td27 field bits<1> SOPC = 0;
63 let TSFlags{7} = SOPC;
305 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
312 let SOPC = 1;
DSIDefines.h24 SOPC = 1 << 7, enumerator
DSIInstrInfo.h224 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
228 return get(Opcode).TSFlags & SIInstrFlags::SOPC; in isSOPC()
DSIInstructions.td326 // SOPC Instructions
DSIInstrInfo.td871 string opName, list<dag> pattern = []> : SOPC <
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td34 field bit SOPC = 0;
130 let TSFlags{4} = SOPC;
DSIDefines.h28 SOPC = 1 << 4, enumerator
DSOPInstructions.td696 // SOPC Instructions
709 class SOPC <bits<7> op, dag outs, dag ins, string asm,
716 let SOPC = 1;
725 string opName, list<dag> pattern = []> : SOPC <
784 def S_SET_GPR_IDX_ON : SOPC <0x11,
DSIInstrInfo.h341 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
345 return get(Opcode).TSFlags & SIInstrFlags::SOPC; in isSOPC()
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DAMDGPUUsage.rst4217 SOPC subsubsection
4227 For full list of supported instructions, refer to "SOPC Instructions" in ISA Manual.
DAMDGPUAsmGFX7.rst468 SOPC chapter
DAMDGPUAsmGFX8.rst487 SOPC chapter
DAMDGPUAsmGFX9.rst639 SOPC chapter