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Searched refs:SRC1 (Results 1 – 17 of 17) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.exp.compr.ll19 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x44003800
28 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x44003800
29 ; GCN: exp mrt0 off, off, [[SRC1]], [[SRC1]] done compr{{$}}
37 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x44003800
38 ; GCN: exp mrt0 [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] done compr{{$}}
46 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x44003800
55 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x44003800
56 ; GCN: exp mrt0 off, [[SRC0]], off, [[SRC1]] done compr{{$}}
74 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x44003800
75 ; GCN: exp mrtz [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] compr{{$}}
[all …]
Dllvm.amdgcn.exp.ll21 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
32 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
35 ; GCN: exp mrt0 off, [[SRC1]], off, off done{{$}}
43 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
54 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
65 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
68 ; GCN: exp mrt0 [[SRC0]], [[SRC1]], off, off done{{$}}
76 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
87 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
100 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
[all …]
Dsminmax.ll78 ; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]]
81 ; GFX9-DAG: v_sub_u32_e32 [[NEG1:v[0-9]+]], 0, [[SRC1:v[0-9]+]]
84 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC1]], [[NEG1]]
144 ; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]]
149 ; GFX9-DAG: v_sub_u32_e32 [[NEG1:v[0-9]+]], 0, [[SRC1:v[0-9]+]]
154 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC1]], [[NEG1]]
Dcombine-ftrunc.ll27 ; GCN: s_load_dwordx2 s{{\[}}[[SRC1:[0-9]+]]:[[SRC2:[0-9]+]]{{\]}}
28 ; GCN-DAG: v_rndne_f32_e32 v[[RND1:[0-9]+]], s[[SRC1]]
Dmul.ll112 ; GCN: s_load_dword [[SRC1:s[0-9]+]],
113 ; GCN: s_mul_i32 [[SRESULT:s[0-9]+]], [[SRC0]], [[SRC1]]
/external/llvm/test/CodeGen/Thumb/
Dcopy_thumb.ll9 ; CHECK-LOLOMOV: mov [[TMP:r[0-7]]], [[SRC1:r[01]]]
10 ; CHECK-LOLOMOV-NEXT: mov [[SRC1]], [[SRC2:r[01]]]
19 ; CHECK-NOLOLOMOV-NOT: mov [[TMP:r[0-7]]], [[SRC1:r[01]]]
20 ; CHECK-NOLOLOMOV: push {[[SRC1:r[01]]]}
22 ; CHECK-NOLOLOMOV-NOT: mov [[TMP:r[0-7]]], [[SRC1:r[01]]]
24 ; CHECK-NOLOLOMOV-NEXT: pop {[[SRC1]]}
25 ; CHECK-NOLOLOMOV-NOT: mov [[TMP:r[0-7]]], [[SRC1:r[01]]]
/external/mesa3d/src/mesa/x86/
Dx86_xform3.S43 #define SRC1 REGOFF(4, ESI) macro
110 FLD_S( SRC1 ) /* F0 F7 F6 F5 F4 */
112 FLD_S( SRC1 ) /* F1 F0 F7 F6 F5 F4 */
114 FLD_S( SRC1 ) /* F2 F1 F0 F7 F6 F5 F4 */
116 FLD_S( SRC1 ) /* F3 F2 F1 F0 F7 F6 F5 F4 */
212 FLD_S( SRC1 ) /* F5 F4 */
296 FLD_S( SRC1 ) /* F0 F6 F5 F4 */
298 FLD_S( SRC1 ) /* F1 F0 F6 F5 F4 */
300 FLD_S( SRC1 ) /* F2 F1 F0 F6 F5 F4 */
387 FLD_S( SRC1 ) /* F1 F4 */
[all …]
Dx86_xform2.S43 #define SRC1 REGOFF(4, ESI) macro
110 FLD_S( SRC1 ) /* F0 F7 F6 F5 F4 */
112 FLD_S( SRC1 ) /* F1 F0 F7 F6 F5 F4 */
114 FLD_S( SRC1 ) /* F2 F1 F0 F7 F6 F5 F4 */
116 FLD_S( SRC1 ) /* F3 F2 F1 F0 F7 F6 F5 F4 */
198 FLD_S( SRC1 ) /* F1 F4 */
265 FLD_S( SRC1 ) /* F0 F6 F5 F4 */
267 FLD_S( SRC1 ) /* F1 F0 F6 F5 F4 */
269 FLD_S( SRC1 ) /* F2 F1 F0 F6 F5 F4 */
346 FLD_S( SRC1 ) /* F1 F4 */
[all …]
Dx86_xform4.S43 #define SRC1 REGOFF(4, ESI) macro
110 FLD_S( SRC1 ) /* F0 F7 F6 F5 F4 */
112 FLD_S( SRC1 ) /* F1 F0 F7 F6 F5 F4 */
114 FLD_S( SRC1 ) /* F2 F1 F0 F7 F6 F5 F4 */
116 FLD_S( SRC1 ) /* F3 F2 F1 F0 F7 F6 F5 F4 */
219 FLD_S( SRC1 ) /* F5 F4 */
306 FLD_S( SRC1 ) /* F0 F6 F5 F4 */
308 FLD_S( SRC1 ) /* F1 F0 F6 F5 F4 */
310 FLD_S( SRC1 ) /* F2 F1 F0 F6 F5 F4 */
405 FLD_S( SRC1 ) /* F5 F4 */
[all …]
Dx86_cliptest.S38 #define SRC1 REGOFF(4, ESI) macro
182 MOV_L( SRC1, EBX )
231 FLD_S( SRC1 ) /* F1 F0 F3 */
348 MOV_L( SRC1, EBX )
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb/
Dcopy_thumb.ll9 ; CHECK-LOLOMOV: mov [[TMP:r[0-7]]], [[SRC1:r[01]]]
10 ; CHECK-LOLOMOV-NEXT: mov [[SRC1]], [[SRC2:r[01]]]
19 ; CHECK-NOLOLOMOV: movs [[TMP:r[0-7]]], [[SRC1:r[01]]]
20 ; CHECK-NOLOLOMOV-NEXT: movs [[SRC1]], [[SRC2:r[01]]]
/external/llvm/test/CodeGen/X86/
Dmachine-cp.ll69 ; CHECK: psllw $7, [[SRC1:%xmm[0-9]+]]
70 ; CHECK-NEXT: pand {{.*}}(%rip), [[SRC1]]
71 ; CHECK-NEXT: pcmpgtb [[SRC1]], [[SRC2:%xmm[0-9]+]]
/external/llvm/test/CodeGen/AMDGPU/
Dsminmax.ll58 ; GCN-DAG: v_sub_i32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]]
61 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[NEG1]], [[SRC1]]
117 ; GCN-DAG: v_sub_i32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]]
122 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[NEG1]], [[SRC1]]
Dmul.ll112 ; SI: s_load_dword [[SRC1:s[0-9]+]],
113 ; SI: s_mul_i32 [[SRESULT:s[0-9]+]], [[SRC0]], [[SRC1]]
/external/webp/src/dsp/
Drescaler_neon.c32 #define STORE_32x8(SRC0, SRC1, DST) do { \ argument
34 vst1q_u32((DST) + 4, SRC1); \
/external/mesa3d/src/freedreno/.gitlab-ci/reference/
Des2gears-a320.log227 { SRC1 = 8272 }
266 { SRC1 = 0 }
624 { SRC1 = 0 }
14480 { SRC1 = 4096 }
14761 { SRC1 = 8272 }
14816 { SRC1 = 4096 }
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/X86/
Dx86-avx512.ll932 ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[SRC1:%.*]], i64 0
947 ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[SRC1:%.*]], i64 0
962 ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[SRC1:%.*]], i64 0
977 ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[SRC1:%.*]], i64 0