1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015 Regents of the University of California 4 * 5 * Taken from Linux arch/riscv/include/asm/csr.h 6 */ 7 8 #ifndef _ASM_RISCV_CSR_H 9 #define _ASM_RISCV_CSR_H 10 11 #include <asm/asm.h> 12 #include <linux/const.h> 13 14 /* Status register flags */ 15 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ 16 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ 17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ 18 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ 19 20 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ 21 #define SR_FS_OFF _AC(0x00000000, UL) 22 #define SR_FS_INITIAL _AC(0x00002000, UL) 23 #define SR_FS_CLEAN _AC(0x00004000, UL) 24 #define SR_FS_DIRTY _AC(0x00006000, UL) 25 26 #define SR_XS _AC(0x00018000, UL) /* Extension Status */ 27 #define SR_XS_OFF _AC(0x00000000, UL) 28 #define SR_XS_INITIAL _AC(0x00008000, UL) 29 #define SR_XS_CLEAN _AC(0x00010000, UL) 30 #define SR_XS_DIRTY _AC(0x00018000, UL) 31 32 #ifndef CONFIG_64BIT 33 #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ 34 #else 35 #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ 36 #endif 37 38 /* SATP flags */ 39 #ifndef CONFIG_64BIT 40 #define SATP_PPN _AC(0x003FFFFF, UL) 41 #define SATP_MODE_32 _AC(0x80000000, UL) 42 #define SATP_MODE SATP_MODE_32 43 #else 44 #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) 45 #define SATP_MODE_39 _AC(0x8000000000000000, UL) 46 #define SATP_MODE SATP_MODE_39 47 #endif 48 49 /* SCAUSE */ 50 #define SCAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) 51 52 #define IRQ_U_SOFT 0 53 #define IRQ_S_SOFT 1 54 #define IRQ_M_SOFT 3 55 #define IRQ_U_TIMER 4 56 #define IRQ_S_TIMER 5 57 #define IRQ_M_TIMER 7 58 #define IRQ_U_EXT 8 59 #define IRQ_S_EXT 9 60 #define IRQ_M_EXT 11 61 62 #define EXC_INST_MISALIGNED 0 63 #define EXC_INST_ACCESS 1 64 #define EXC_BREAKPOINT 3 65 #define EXC_LOAD_ACCESS 5 66 #define EXC_STORE_ACCESS 7 67 #define EXC_SYSCALL 8 68 #define EXC_INST_PAGE_FAULT 12 69 #define EXC_LOAD_PAGE_FAULT 13 70 #define EXC_STORE_PAGE_FAULT 15 71 72 /* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */ 73 #define MIE_MSIE (_AC(0x1, UL) << IRQ_M_SOFT) 74 #define SIE_SSIE (_AC(0x1, UL) << IRQ_S_SOFT) 75 #define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER) 76 #define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT) 77 78 #define CSR_FCSR 0x003 79 #define CSR_CYCLE 0xc00 80 #define CSR_TIME 0xc01 81 #define CSR_INSTRET 0xc02 82 #define CSR_SSTATUS 0x100 83 #define CSR_SIE 0x104 84 #define CSR_STVEC 0x105 85 #define CSR_SCOUNTEREN 0x106 86 #define CSR_SSCRATCH 0x140 87 #define CSR_SEPC 0x141 88 #define CSR_SCAUSE 0x142 89 #define CSR_STVAL 0x143 90 #define CSR_SIP 0x144 91 #define CSR_SATP 0x180 92 #define CSR_MSTATUS 0x300 93 #define CSR_MISA 0x301 94 #define CSR_MIE 0x304 95 #define CSR_MTVEC 0x305 96 #define CSR_MCOUNTEREN 0x306 97 #define CSR_MSCRATCH 0x340 98 #define CSR_MEPC 0x341 99 #define CSR_MCAUSE 0x342 100 #define CSR_MTVAL 0x343 101 #define CSR_MIP 0x344 102 #define CSR_CYCLEH 0xc80 103 #define CSR_TIMEH 0xc81 104 #define CSR_INSTRETH 0xc82 105 #define CSR_MHARTID 0xf14 106 107 #ifndef __ASSEMBLY__ 108 109 #define csr_swap(csr, val) \ 110 ({ \ 111 unsigned long __v = (unsigned long)(val); \ 112 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ 113 : "=r" (__v) : "rK" (__v) \ 114 : "memory"); \ 115 __v; \ 116 }) 117 118 #define csr_read(csr) \ 119 ({ \ 120 register unsigned long __v; \ 121 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ 122 : "=r" (__v) : \ 123 : "memory"); \ 124 __v; \ 125 }) 126 127 #define csr_write(csr, val) \ 128 ({ \ 129 unsigned long __v = (unsigned long)(val); \ 130 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ 131 : : "rK" (__v) \ 132 : "memory"); \ 133 }) 134 135 #define csr_read_set(csr, val) \ 136 ({ \ 137 unsigned long __v = (unsigned long)(val); \ 138 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ 139 : "=r" (__v) : "rK" (__v) \ 140 : "memory"); \ 141 __v; \ 142 }) 143 144 #define csr_set(csr, val) \ 145 ({ \ 146 unsigned long __v = (unsigned long)(val); \ 147 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ 148 : : "rK" (__v) \ 149 : "memory"); \ 150 }) 151 152 #define csr_read_clear(csr, val) \ 153 ({ \ 154 unsigned long __v = (unsigned long)(val); \ 155 __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ 156 : "=r" (__v) : "rK" (__v) \ 157 : "memory"); \ 158 __v; \ 159 }) 160 161 #define csr_clear(csr, val) \ 162 ({ \ 163 unsigned long __v = (unsigned long)(val); \ 164 __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ 165 : : "rK" (__v) \ 166 : "memory"); \ 167 }) 168 169 #endif /* __ASSEMBLY__ */ 170 171 #endif /* _ASM_RISCV_CSR_H */ 172