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Searched refs:SReg (Results 1 – 24 of 24) sorted by relevance

/external/llvm/lib/CodeGen/
DRegisterScavenging.cpp373 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI); in scavengeRegister() local
376 if (!isRegUsed(SReg)) { in scavengeRegister()
377 DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n"); in scavengeRegister()
378 return SReg; in scavengeRegister()
420 Scavenged[SI].Reg = SReg; in scavengeRegister()
424 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) { in scavengeRegister()
429 TRI->getName(SReg) + " from class " + TRI->getRegClassName(RC) + in scavengeRegister()
433 TII->storeRegToStackSlot(*MBB, I, SReg, true, Scavenged[SI].FrameIndex, in scavengeRegister()
441 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, Scavenged[SI].FrameIndex, in scavengeRegister()
454 DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) << in scavengeRegister()
[all …]
DBranchFolding.cpp414 for (MCSuperRegIterator SReg(Reg, TRI); SReg.isValid(); ++SReg) { in computeLiveIns() local
415 if (LiveRegs.contains(*SReg)) { in computeLiveIns()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DRegisterScavenging.cpp560 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI); in scavengeRegister() local
563 if (!isRegUsed(SReg)) { in scavengeRegister()
564 LLVM_DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n"); in scavengeRegister()
565 return SReg; in scavengeRegister()
568 ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI); in scavengeRegister()
572 << printReg(SReg, TRI) << "\n"); in scavengeRegister()
574 return SReg; in scavengeRegister()
660 unsigned SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(), in scavengeVReg() local
662 MRI.replaceRegWith(VReg, SReg); in scavengeVReg()
664 return SReg; in scavengeVReg()
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DLivePhysRegs.cpp268 for (MCSuperRegIterator SReg(Reg, &TRI); SReg.isValid(); ++SReg) { in addLiveIns() local
269 if (LiveRegs.contains(*SReg) && !MRI.isReserved(*SReg)) { in addLiveIns()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp101 unsigned getDPRLaneFromSPR(unsigned SReg);
116 unsigned getPrefSPRLane(unsigned SReg);
145 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) { in getDPRLaneFromSPR() argument
146 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR()
154 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) { in getPrefSPRLane() argument
155 if (!TRI->isVirtualRegister(SReg)) in getPrefSPRLane()
156 return getDPRLaneFromSPR(SReg); in getPrefSPRLane()
158 MachineInstr *MI = MRI->getVRegDef(SReg); in getPrefSPRLane()
160 MachineOperand *MO = MI->findRegisterDefOperand(SReg); in getPrefSPRLane()
167 SReg = MI->getOperand(1).getReg(); in getPrefSPRLane()
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DARMBaseInstrInfo.cpp4613 unsigned SReg, unsigned &Lane) { in getCorrespondingDRegAndLane() argument
4614 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
4621 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
/external/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp103 unsigned getDPRLaneFromSPR(unsigned SReg);
118 unsigned getPrefSPRLane(unsigned SReg);
147 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) { in getDPRLaneFromSPR() argument
148 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR()
156 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) { in getPrefSPRLane() argument
157 if (!TRI->isVirtualRegister(SReg)) in getPrefSPRLane()
158 return getDPRLaneFromSPR(SReg); in getPrefSPRLane()
160 MachineInstr *MI = MRI->getVRegDef(SReg); in getPrefSPRLane()
162 MachineOperand *MO = MI->findRegisterDefOperand(SReg); in getPrefSPRLane()
169 SReg = MI->getOperand(1).getReg(); in getPrefSPRLane()
[all …]
DARMBaseInstrInfo.cpp4218 unsigned SReg, unsigned &Lane) { in getCorrespondingDRegAndLane() argument
4219 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
4226 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DVirtRegMap.h134 void setIsSplitFromReg(unsigned virtReg, unsigned SReg) { in setIsSplitFromReg() argument
135 Virt2SplitMap[virtReg] = SReg; in setIsSplitFromReg()
/external/llvm/lib/Target/AMDGPU/
DSIShrinkInstructions.cpp352 unsigned SReg = Src2->getReg(); in runOnMachineFunction() local
353 if (TargetRegisterInfo::isVirtualRegister(SReg)) { in runOnMachineFunction()
354 MRI.setRegAllocationHint(SReg, 0, AMDGPU::VCC); in runOnMachineFunction()
357 if (SReg != AMDGPU::VCC) in runOnMachineFunction()
DSIInstructions.td2867 // FIXME: Why do only some of these type combinations for SReg and
/external/llvm/include/llvm/CodeGen/
DVirtRegMap.h138 void setIsSplitFromReg(unsigned virtReg, unsigned SReg) { in setIsSplitFromReg() argument
139 Virt2SplitMap[virtReg] = SReg; in setIsSplitFromReg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIShrinkInstructions.cpp454 unsigned SReg = Src2->getReg(); in runOnMachineFunction() local
455 if (TargetRegisterInfo::isVirtualRegister(SReg)) { in runOnMachineFunction()
456 MRI.setRegAllocationHint(SReg, 0, AMDGPU::VCC); in runOnMachineFunction()
459 if (SReg != AMDGPU::VCC) in runOnMachineFunction()
DSIInstrInfo.cpp690 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass); in insertVectorSelect() local
691 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg) in insertVectorSelect()
696 .addReg(SReg); in insertVectorSelect()
701 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass); in insertVectorSelect() local
702 BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg) in insertVectorSelect()
708 .addReg(SReg); in insertVectorSelect()
712 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass); in insertVectorSelect() local
713 BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg) in insertVectorSelect()
719 .addReg(SReg); in insertVectorSelect()
725 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass); in insertVectorSelect() local
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DSIRegisterInfo.td625 defm SSrc : RegImmOperand<"SReg", "SSrc">;
631 defm SCSrc : RegInlineOperand<"SReg", "SCSrc"> ;
DSIInstructions.td833 // FIXME: Why do only some of these type combinations for SReg and
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp3387 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotation() local
3396 if (DReg == SReg) { in expandRotation()
3404 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); in expandRotation()
3409 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
3436 TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI); in expandRotation()
3437 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
3452 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotationImm() local
3465 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI); in expandRotationImm()
3470 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI); in expandRotationImm()
3480 TOut.emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandRotationImm()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp979 SReg = MF.getRegInfo().createVirtualRegister(RC); in eliminateFrameIndex() local
983 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg) in eliminateFrameIndex()
988 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) in eliminateFrameIndex()
1013 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); in eliminateFrameIndex()
DPPCISelLowering.cpp9918 unsigned SReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
9919 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), SReg) in EmitPartwordAtomicBinary()
9921 unsigned ValueReg = SReg; in EmitPartwordAtomicBinary()
9926 .addReg(SReg).addReg(ShiftReg); in EmitPartwordAtomicBinary()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp4415 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotation() local
4423 if (DReg == SReg) { in expandRotation()
4431 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); in expandRotation()
4436 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4462 TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI); in expandRotation()
4463 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4478 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotationImm() local
4490 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI); in expandRotationImm()
4495 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI); in expandRotationImm()
4504 TOut.emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandRotationImm()
[all …]
/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
DMemRegion.h1080 const MemRegion *SReg) in CXXBaseObjectRegion() argument
1081 : TypedValueRegion(SReg, CXXBaseObjectRegionKind), Data(RD, IsVirtual) {} in CXXBaseObjectRegion()
1084 bool IsVirtual, const MemRegion *SReg);
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp888 SReg = MF.getRegInfo().createVirtualRegister(RC); in eliminateFrameIndex() local
893 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) in eliminateFrameIndex()
917 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); in eliminateFrameIndex()
/external/clang/lib/StaticAnalyzer/Core/
DMemRegion.cpp409 const MemRegion *SReg) { in ProfileRegion() argument
412 ID.AddPointer(SReg); in ProfileRegion()
/external/swiftshader/third_party/subzero/src/
DIceAssemblerARM32.cpp205 IValueT SReg = EncodedQReg << 2; in mapQRegToSReg() local
206 assert(SReg < RegARM32::getNumSRegs()); in mapQRegToSReg()
207 return SReg; in mapQRegToSReg()