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Searched refs:SSCG_PLL_OUTPUT_DIV_VAL (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-imx/imx8m/
Dclock_imx8mq.c597 val |= SSCG_PLL_OUTPUT_DIV_VAL(0); in dram_pll_init()
609 val |= SSCG_PLL_OUTPUT_DIV_VAL(1); in dram_pll_init()
621 val |= SSCG_PLL_OUTPUT_DIV_VAL(1); in dram_pll_init()
633 val |= SSCG_PLL_OUTPUT_DIV_VAL(3); in dram_pll_init()
/external/u-boot/arch/arm/include/asm/arch-imx8m/
Dclock_imx8mq.h382 #define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \ macro