Searched refs:STIMER1_CHN_BASE (Results 1 – 2 of 2) sorted by relevance
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/secure/ |
D | secure.c | 111 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff); in sram_secure_timer_init() 112 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff); in sram_secure_timer_init() 114 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); in sram_secure_timer_init() 115 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); in sram_secure_timer_init() 118 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, in sram_secure_timer_init() 124 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff); in secure_timer_init() 125 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff); in secure_timer_init() 127 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); in secure_timer_init() 128 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); in secure_timer_init() 131 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, in secure_timer_init()
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D | secure.h | 68 #define STIMER1_CHN_BASE(n) (STIME_BASE + 0x8000 + 0x20 * (n)) macro
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