1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017-2019 NXP 4 * Copyright 2015 Freescale Semiconductor 5 */ 6 7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ 8 #define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ 9 10 #ifndef __ASSEMBLY__ 11 #include <linux/types.h> 12 #ifdef CONFIG_FSL_LSCH2 13 #include <asm/arch/immap_lsch2.h> 14 #endif 15 #ifdef CONFIG_FSL_LSCH3 16 #include <asm/arch/immap_lsch3.h> 17 #endif 18 #endif 19 20 #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE 21 #define gur_in32(a) in_le32(a) 22 #define gur_out32(a, v) out_le32(a, v) 23 #elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE) 24 #define gur_in32(a) in_be32(a) 25 #define gur_out32(a, v) out_be32(a, v) 26 #endif 27 28 #ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE 29 #define scfg_in32(a) in_le32(a) 30 #define scfg_out32(a, v) out_le32(a, v) 31 #define scfg_clrbits32(addr, clear) clrbits_le32(addr, clear) 32 #define scfg_clrsetbits32(addr, clear, set) clrsetbits_le32(addr, clear, set) 33 #elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE) 34 #define scfg_in32(a) in_be32(a) 35 #define scfg_out32(a, v) out_be32(a, v) 36 #define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear) 37 #define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set) 38 #endif 39 40 #ifdef CONFIG_SYS_FSL_PEX_LUT_LE 41 #define pex_lut_in32(a) in_le32(a) 42 #define pex_lut_out32(a, v) out_le32(a, v) 43 #elif defined(CONFIG_SYS_FSL_PEX_LUT_BE) 44 #define pex_lut_in32(a) in_be32(a) 45 #define pex_lut_out32(a, v) out_be32(a, v) 46 #endif 47 #ifndef __ASSEMBLY__ 48 struct cpu_type { 49 char name[15]; 50 u32 soc_ver; 51 u32 num_cores; 52 }; 53 54 #define CPU_TYPE_ENTRY(n, v, nc) \ 55 { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} 56 57 #ifdef CONFIG_TFABOOT 58 #define SMC_DRAM_BANK_INFO (0xC200FF12) 59 #define SIP_SVC_RCW 0xC200FF18 60 61 phys_size_t tfa_get_dram_size(void); 62 63 enum boot_src { 64 BOOT_SOURCE_RESERVED = 0, 65 BOOT_SOURCE_IFC_NOR, 66 BOOT_SOURCE_IFC_NAND, 67 BOOT_SOURCE_QSPI_NOR, 68 BOOT_SOURCE_QSPI_NAND, 69 BOOT_SOURCE_XSPI_NOR, 70 BOOT_SOURCE_XSPI_NAND, 71 BOOT_SOURCE_SD_MMC, 72 BOOT_SOURCE_SD_MMC2, 73 BOOT_SOURCE_I2C1_EXTENDED, 74 }; 75 76 enum boot_src get_boot_src(void); 77 #endif 78 #endif 79 #define SVR_WO_E 0xFFFFFE 80 #define SVR_LS1012A 0x870400 81 #define SVR_LS1043A 0x879200 82 #define SVR_LS1023A 0x879208 83 /* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ 84 #define SVR_LS1043A_P23 0x879202 85 #define SVR_LS1023A_P23 0x87920A 86 #define SVR_LS1017A 0x870B24 87 #define SVR_LS1018A 0x870B20 88 #define SVR_LS1027A 0x870B04 89 #define SVR_LS1028A 0x870B00 90 #define SVR_LS1046A 0x870700 91 #define SVR_LS1026A 0x870708 92 #define SVR_LS1048A 0x870320 93 #define SVR_LS1084A 0x870302 94 #define SVR_LS1088A 0x870300 95 #define SVR_LS1044A 0x870322 96 #define SVR_LS2045A 0x870120 97 #define SVR_LS2080A 0x870110 98 #define SVR_LS2085A 0x870100 99 #define SVR_LS2040A 0x870130 100 #define SVR_LS2088A 0x870900 101 #define SVR_LS2084A 0x870910 102 #define SVR_LS2048A 0x870920 103 #define SVR_LS2044A 0x870930 104 #define SVR_LS2081A 0x870918 105 #define SVR_LS2041A 0x870914 106 #define SVR_LX2160A 0x873600 107 #define SVR_LX2120A 0x873620 108 #define SVR_LX2080A 0x873602 109 110 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) 111 #define SVR_MIN(svr) (((svr) >> 0) & 0xf) 112 #define SVR_REV(svr) (((svr) >> 0) & 0xff) 113 #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) 114 #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) 115 #ifdef CONFIG_ARCH_LX2160A 116 #define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1)) 117 #endif 118 #ifdef CONFIG_ARCH_LS1028A 119 #define IS_MULTIMEDIA_EN(svr) (!((svr >> 10) & 0x1)) 120 #endif 121 #define IS_SVR_REV(svr, maj, min) \ 122 ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) 123 #define SVR_DEV(svr) ((svr) >> 8) 124 #define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev)) 125 126 #ifndef __ASSEMBLY__ 127 #ifdef CONFIG_FSL_LSCH3 128 void fsl_lsch3_early_init_f(void); 129 int get_core_volt_from_fuse(void); 130 #elif defined(CONFIG_FSL_LSCH2) 131 void fsl_lsch2_early_init_f(void); 132 int setup_chip_volt(void); 133 /* Setup core vdd in unit mV */ 134 int board_setup_core_volt(u32 vdd); 135 #ifdef CONFIG_FSL_PFE 136 void init_pfe_scfg_dcfg_regs(void); 137 #endif 138 #endif 139 #ifdef CONFIG_QSPI_AHB_INIT 140 int qspi_ahb_init(void); 141 #endif 142 143 void cpu_name(char *name); 144 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 145 void erratum_a009635(void); 146 #endif 147 148 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 149 void erratum_a010315(void); 150 #endif 151 152 bool soc_has_dp_ddr(void); 153 bool soc_has_aiop(void); 154 #endif 155 156 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ 157