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Searched refs:SrcLo (Results 1 – 11 of 11) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRInstrInfo.cpp56 unsigned DestLo, DestHi, SrcLo, SrcHi; in copyPhysReg() local
59 TRI.splitReg(SrcReg, SrcLo, SrcHi); in copyPhysReg()
63 .addReg(SrcLo, getKillRegState(KillSrc)); in copyPhysReg()
/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp566 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); in expandPseudoMTLoHi() local
580 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill())); in expandPseudoMTLoHi()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp724 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); in expandPseudoMTLoHi() local
738 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill())); in expandPseudoMTLoHi()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonFrameLowering.cpp1719 unsigned SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo); in expandStoreVec2() local
1730 if (LPR.contains(SrcLo)) { in expandStoreVec2()
1736 .addReg(SrcLo, getKillRegState(IsKill)) in expandStoreVec2()
DHexagonInstrInfo.cpp1292 unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo() local
1299 .addReg(SrcLo); in expandPostRAPseudo()
1305 unsigned SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo() local
1311 .addReg(SrcLo); in expandPostRAPseudo()
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.cpp1278 unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::subreg_loreg); in expandPostRAPseudo() local
1284 .addReg(SrcLo); in expandPostRAPseudo()
1285 SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::subreg_loreg); in expandPostRAPseudo()
1291 .addReg(SrcLo); in expandPostRAPseudo()
DHexagonFrameLowering.cpp1550 unsigned SrcLo = HRI.getSubReg(SrcR, Hexagon::subreg_loreg); in expandStoreVec2() local
1574 .addReg(SrcLo, getKillRegState(IsKill)) in expandStoreVec2()
/external/swiftshader/third_party/subzero/src/
DIceTargetLoweringX86BaseImpl.h6782 Operand *SrcLo = loOperand(Src);
6787 _mov(T_Lo, SrcLo);
7300 Operand *SrcLo = legalize(loOperand(Src), Legal_Reg | Legal_Imm);
7309 _add_rmw(AddrLo, SrcLo);
7313 _sub_rmw(AddrLo, SrcLo);
7317 _and_rmw(AddrLo, SrcLo);
7321 _or_rmw(AddrLo, SrcLo);
7325 _xor_rmw(AddrLo, SrcLo);
DIceInstARM32.cpp1931 auto *SrcLo = llvm::cast<Variable>(getSrc(0)); in emitSingleDestMultiSource() local
1935 assert(SrcLo->hasReg()); in emitSingleDestMultiSource()
1943 SrcLo->emit(Func); in emitSingleDestMultiSource()
DIceTargetLoweringARM32.h321 void div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi);
DIceTargetLoweringARM32.cpp2289 void TargetARM32::div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi) { in div0Check() argument
2290 if (isGuaranteedNonzeroInt(SrcLo) || isGuaranteedNonzeroInt(SrcHi)) in div0Check()
2292 Variable *SrcLoReg = legalizeToReg(SrcLo); in div0Check()