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Searched refs:SrcOp (Results 1 – 25 of 38) sorted by relevance

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/external/tensorflow/tensorflow/compiler/mlir/xla/transforms/
Dmaterialize_broadcasts.cc49 template <typename SrcOp>
50 bool CreateBroadcastsForBinaryOp(SrcOp op, PatternRewriter *rewriter, in CreateBroadcastsForBinaryOp()
121 template <typename SrcOp>
122 struct BinaryOpWithBroadcastConvert : public OpRewritePattern<SrcOp> {
124 : OpRewritePattern<SrcOp>(context) {} in BinaryOpWithBroadcastConvert()
126 PatternMatchResult matchAndRewrite(SrcOp op, in matchAndRewrite()
136 rewriter.replaceOpWithNewOp<SrcOp>(op, op.getType(), new_lhs, new_rhs, in matchAndRewrite()
/external/llvm/lib/Linker/
DIRMover.cpp1045 MDNode *SrcOp = SrcModFlags->getOperand(I); in linkModuleFlagsMetadata() local
1047 mdconst::extract<ConstantInt>(SrcOp->getOperand(0)); in linkModuleFlagsMetadata()
1048 MDString *ID = cast<MDString>(SrcOp->getOperand(1)); in linkModuleFlagsMetadata()
1058 if (Requirements.insert(cast<MDNode>(SrcOp->getOperand(2)))) { in linkModuleFlagsMetadata()
1059 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1066 Flags[ID] = std::make_pair(SrcOp, DstModFlags->getNumOperands()); in linkModuleFlagsMetadata()
1067 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1080 SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
1086 DstModFlags->setOperand(DstIndex, SrcOp); in linkModuleFlagsMetadata()
1087 Flags[ID].first = SrcOp; in linkModuleFlagsMetadata()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Linker/
DIRMover.cpp1153 MDNode *SrcOp = SrcModFlags->getOperand(I); in linkModuleFlagsMetadata() local
1155 mdconst::extract<ConstantInt>(SrcOp->getOperand(0)); in linkModuleFlagsMetadata()
1156 MDString *ID = cast<MDString>(SrcOp->getOperand(1)); in linkModuleFlagsMetadata()
1166 if (Requirements.insert(cast<MDNode>(SrcOp->getOperand(2)))) { in linkModuleFlagsMetadata()
1167 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1174 Flags[ID] = std::make_pair(SrcOp, DstModFlags->getNumOperands()); in linkModuleFlagsMetadata()
1175 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1185 DstModFlags->setOperand(DstIndex, SrcOp); in linkModuleFlagsMetadata()
1186 Flags[ID].first = SrcOp; in linkModuleFlagsMetadata()
1193 SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSILowerControlFlow.cpp455 for (const auto &SrcOp : Def->explicit_operands()) in findMaskOperands() local
456 if (SrcOp.isReg() && SrcOp.isUse() && in findMaskOperands()
457 (TargetRegisterInfo::isVirtualRegister(SrcOp.getReg()) || in findMaskOperands()
458 SrcOp.getReg() == AMDGPU::EXEC)) in findMaskOperands()
459 Src.push_back(SrcOp); in findMaskOperands()
DSIPeepholeSDWA.cpp161 const MachineOperand *SrcOp) const;
334 const MachineOperand *SrcOp) const { in getSrcMods()
336 const auto *MI = SrcOp->getParent(); in getSrcMods()
337 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) { in getSrcMods()
341 } else if (TII->getNamedOperand(*MI, AMDGPU::OpName::src1) == SrcOp) { in getSrcMods()
DSIInstrInfo.cpp1198 const MachineOperand &SrcOp = MI.getOperand(1); in expandPostRAPseudo() local
1200 assert(!SrcOp.isFPImm()); in expandPostRAPseudo()
1201 if (SrcOp.isImm()) { in expandPostRAPseudo()
1202 APInt Imm(64, SrcOp.getImm()); in expandPostRAPseudo()
1210 assert(SrcOp.isReg()); in expandPostRAPseudo()
1212 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0)) in expandPostRAPseudo()
1215 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1)) in expandPostRAPseudo()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonExpandCondsets.cpp213 MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
623 MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp, in genCondTfrFor() argument
627 MachineInstr *MI = SrcOp.getParent(); in genCondTfrFor()
637 unsigned Opc = getCondTfrOpcode(SrcOp, PredSense); in genCondTfrFor()
642 if (SrcOp.isReg()) { in genCondTfrFor()
643 unsigned SrcState = getRegState(SrcOp); in genCondTfrFor()
644 if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR)) in genCondTfrFor()
649 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg()); in genCondTfrFor()
654 .add(SrcOp); in genCondTfrFor()
DHexagonRDFOpt.cpp139 const MachineOperand &SrcOp = MI->getOperand(1); in INITIALIZE_PASS_DEPENDENCY() local
141 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
DHexagonFrameLowering.cpp2221 MachineOperand &SrcOp = SI.getOperand(2); in optimizeSpillSlots() local
2223 HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(), in optimizeSpillSlots()
2224 SrcOp.getSubReg() }; in optimizeSpillSlots()
2246 .add(SrcOp); in optimizeSpillSlots()
2253 if (unsigned SR = SrcOp.getSubReg()) in optimizeSpillSlots()
2254 SrcOp.setReg(HRI.getSubReg(FoundR, SR)); in optimizeSpillSlots()
2256 SrcOp.setReg(FoundR); in optimizeSpillSlots()
2257 SrcOp.setSubReg(0); in optimizeSpillSlots()
2259 SrcOp.setIsKill(false); in optimizeSpillSlots()
/external/llvm/lib/Target/Hexagon/
DHexagonRDFOpt.cpp123 const MachineOperand &SrcOp = MI->getOperand(1); in interpretAsCopy() local
125 { SrcOp.getReg(), SrcOp.getSubReg() }); in interpretAsCopy()
DHexagonFrameLowering.cpp2108 MachineOperand &SrcOp = SI->getOperand(2); in optimizeSpillSlots() local
2110 HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(), in optimizeSpillSlots()
2111 SrcOp.getSubReg() }; in optimizeSpillSlots()
2112 auto *RC = getRegClass({SrcOp.getReg(), SrcOp.getSubReg()}); in optimizeSpillSlots()
2125 .addOperand(SrcOp); in optimizeSpillSlots()
2132 if (unsigned SR = SrcOp.getSubReg()) in optimizeSpillSlots()
2133 SrcOp.setReg(HRI.getSubReg(FoundR, SR)); in optimizeSpillSlots()
2135 SrcOp.setReg(FoundR); in optimizeSpillSlots()
2136 SrcOp.setSubReg(0); in optimizeSpillSlots()
2138 SrcOp.setIsKill(false); in optimizeSpillSlots()
DHexagonExpandCondsets.cpp249 MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
611 MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp, in genCondTfrFor() argument
615 MachineInstr *MI = SrcOp.getParent(); in genCondTfrFor()
625 unsigned Opc = getCondTfrOpcode(SrcOp, PredSense); in genCondTfrFor()
630 .addOperand(SrcOp); in genCondTfrFor()
/external/llvm/utils/TableGen/
DCodeGenInstruction.cpp244 std::pair<unsigned,unsigned> SrcOp = Ops.ParseOperandName(SrcOpName, false); in ParseConstraint() local
245 if (SrcOp > DestOp) { in ParseConstraint()
246 std::swap(SrcOp, DestOp); in ParseConstraint()
250 unsigned FlatOpNo = Ops.getFlattenedOperandNumber(SrcOp); in ParseConstraint()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenInstruction.cpp245 std::pair<unsigned,unsigned> SrcOp = Ops.ParseOperandName(SrcOpName, false); in ParseConstraint() local
246 if (SrcOp > DestOp) { in ParseConstraint()
247 std::swap(SrcOp, DestOp); in ParseConstraint()
251 unsigned FlatOpNo = Ops.getFlattenedOperandNumber(SrcOp); in ParseConstraint()
/external/llvm/lib/Target/X86/
DX86MCInstLower.cpp1467 const MachineOperand &SrcOp = MI->getOperand(SrcIdx); in EmitInstruction() local
1474 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask)); in EmitInstruction()
1489 const MachineOperand &SrcOp = MI->getOperand(1); in EmitInstruction() local
1496 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask)); in EmitInstruction()
1511 const MachineOperand &SrcOp = MI->getOperand(1); in EmitInstruction() local
1518 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask)); in EmitInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/InstCombine/
DInstructionCombining.cpp1949 Value *SrcOp = BCI->getOperand(0); in visitGetElementPtrInst() local
1966 GEP.setOperand(0, SrcOp); in visitGetElementPtrInst()
1978 if (!isa<BitCastInst>(SrcOp) && GEP.accumulateConstantOffset(DL, Offset)) { in visitGetElementPtrInst()
1984 if (isa<AllocaInst>(SrcOp) || isAllocationFn(SrcOp, &TLI)) { in visitGetElementPtrInst()
1997 return new AddrSpaceCastInst(SrcOp, GEPType); in visitGetElementPtrInst()
1998 return new BitCastInst(SrcOp, GEPType); in visitGetElementPtrInst()
2008 ? Builder.CreateInBoundsGEP(nullptr, SrcOp, NewIndices) in visitGetElementPtrInst()
2009 : Builder.CreateGEP(nullptr, SrcOp, NewIndices); in visitGetElementPtrInst()
DInstCombineCasts.cpp1083 if (auto *SrcOp = dyn_cast<Instruction>(Src)) in visitZExt() local
1084 if (SrcOp->hasOneUse()) in visitZExt()
1085 replaceAllDbgUsesWith(*SrcOp, *Res, CI, DT); in visitZExt()
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp861 const MachineOperand &SrcOp = MI.getOperand(1); in expandPostRAPseudo() local
863 assert(!SrcOp.isFPImm()); in expandPostRAPseudo()
864 if (SrcOp.isImm()) { in expandPostRAPseudo()
865 APInt Imm(64, SrcOp.getImm()); in expandPostRAPseudo()
873 assert(SrcOp.isReg()); in expandPostRAPseudo()
875 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0)) in expandPostRAPseudo()
878 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1)) in expandPostRAPseudo()
/external/llvm/lib/Analysis/
DInstructionSimplify.cpp2452 Value *SrcOp = LI->getOperand(0); in SimplifyICmpInst() local
2453 Type *SrcTy = SrcOp->getType(); in SimplifyICmpInst()
2462 if (Value *V = SimplifyICmpInst(Pred, SrcOp, in SimplifyICmpInst()
2469 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0), in SimplifyICmpInst()
2482 SrcOp, RI->getOperand(0), Q, in SimplifyICmpInst()
2498 SrcOp, Trunc, Q, MaxRecurse-1)) in SimplifyICmpInst()
2541 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0), in SimplifyICmpInst()
2556 if (Value *V = SimplifyICmpInst(Pred, SrcOp, Trunc, Q, MaxRecurse-1)) in SimplifyICmpInst()
2588 if (Value *V = SimplifyICmpInst(ICmpInst::ICMP_SLT, SrcOp, in SimplifyICmpInst()
2597 if (Value *V = SimplifyICmpInst(ICmpInst::ICMP_SGE, SrcOp, in SimplifyICmpInst()
/external/llvm/tools/llvm-c-test/
Decho.cpp429 LLVMValueRef SrcOp = LLVMGetOperand(Src, 0); in CloneInstruction() local
430 LLVMBasicBlockRef SrcBB = LLVMValueAsBasicBlock(SrcOp); in CloneInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/
DInstructionSimplify.cpp3242 Value *SrcOp = LI->getOperand(0); in SimplifyICmpInst() local
3243 Type *SrcTy = SrcOp->getType(); in SimplifyICmpInst()
3252 if (Value *V = SimplifyICmpInst(Pred, SrcOp, in SimplifyICmpInst()
3259 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0), in SimplifyICmpInst()
3272 SrcOp, RI->getOperand(0), Q, in SimplifyICmpInst()
3288 SrcOp, Trunc, Q, MaxRecurse-1)) in SimplifyICmpInst()
3331 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0), in SimplifyICmpInst()
3346 if (Value *V = SimplifyICmpInst(Pred, SrcOp, Trunc, Q, MaxRecurse-1)) in SimplifyICmpInst()
3378 if (Value *V = SimplifyICmpInst(ICmpInst::ICMP_SLT, SrcOp, in SimplifyICmpInst()
3387 if (Value *V = SimplifyICmpInst(ICmpInst::ICMP_SGE, SrcOp, in SimplifyICmpInst()
/external/llvm/lib/Transforms/Vectorize/
DLoopVectorize.cpp2628 for (Value *SrcOp : Instr->operands()) { in scalarizeInstruction()
2630 if (SrcOp == OldInduction) { in scalarizeInstruction()
2631 Params.push_back(getVectorValue(SrcOp)); in scalarizeInstruction()
2636 auto *SrcInst = dyn_cast<Instruction>(SrcOp); in scalarizeInstruction()
2647 Scalars.append(UF, SrcOp); in scalarizeInstruction()
6229 for (Value *SrcOp : Instr->operands()) { in scalarizeInstruction()
6231 if (SrcOp == OldInduction) { in scalarizeInstruction()
6232 Params.push_back(getVectorValue(SrcOp)); in scalarizeInstruction()
6237 Instruction *SrcInst = dyn_cast<Instruction>(SrcOp); in scalarizeInstruction()
6248 Scalars.append(UF, SrcOp); in scalarizeInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMachineVerifier.cpp1045 const MachineOperand &SrcOp = MI->getOperand(1); in visitMachineInstrBefore() local
1047 LLT SrcTy = MRI->getType(SrcOp.getReg()); in visitMachineInstrBefore()
1058 unsigned SrcSize = TRI->getRegSizeInBits(SrcOp.getReg(), *MRI); in visitMachineInstrBefore()
1063 if (!DstOp.getSubReg() && !SrcOp.getSubReg()) { in visitMachineInstrBefore()
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-c-test/
Decho.cpp449 LLVMValueRef SrcOp = LLVMGetOperand(Src, 0); in CloneInstruction() local
450 LLVMBasicBlockRef SrcBB = LLVMValueAsBasicBlock(SrcOp); in CloneInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp552 for (SDValue SrcOp : Op->ops()) { in SimplifyDemandedBits() local
553 if (!isa<ConstantSDNode>(SrcOp)) { in SimplifyDemandedBits()
558 Known2.One = cast<ConstantSDNode>(SrcOp)->getAPIntValue(); in SimplifyDemandedBits()
1432 SDValue SrcOp = Op.getOperand(i); in SimplifyDemandedVectorElts() local
1433 if (SrcOp.isUndef()) { in SimplifyDemandedVectorElts()
1435 } else if (EltSizeInBits == SrcOp.getScalarValueSizeInBits() && in SimplifyDemandedVectorElts()
1436 (isNullConstant(SrcOp) || isNullFPConstant(SrcOp))) { in SimplifyDemandedVectorElts()

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