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Searched refs:Sub1 (Results 1 – 22 of 22) sorted by relevance

/external/tensorflow/tensorflow/python/kernel_tests/distributions/
Dkullback_leibler_test.py101 class Sub1(normal.Normal): class
111 class Sub11(Sub1):
117 @kullback_leibler.RegisterKL(Sub1, Sub1)
121 @kullback_leibler.RegisterKL(Sub1, Sub2)
125 @kullback_leibler.RegisterKL(Sub2, Sub1)
131 sub1 = Sub1(loc=0.0, scale=1.0)
/external/snakeyaml/src/test/java/org/yaml/snakeyaml/ruby/
DTestObject.java19 private Sub1 sub1;
22 public Sub1 getSub1() { in getSub1()
26 public void setSub1(Sub1 sub1) { in setSub1()
DRubyTest.java62 repr.addClassTag(Sub1.class, new Tag("!ruby/object:Test::Module::Sub1")); in testEmitWithTags()
85 repr.addClassTag(Sub1.class, new Tag("!ruby/object:Test::Module::Sub1")); in testEmitWithTags2WithoutTagForParentJavabean()
107 con.addTypeDescription(new TypeDescription(Sub1.class, "!ruby/object:Test::Module::Sub1")); in parseObject()
DSub1.java20 public class Sub1 { class
/external/clang/test/SemaTemplate/
Dinstantiate-subscript.cpp8 struct Sub1 { struct
25 template struct Subscript0<Sub1, ConvertibleToInt, long&>;
26 template struct Subscript0<Sub1, Sub0, long&>; // expected-note{{instantiation}}
/external/clang/test/CodeGenObjC/
Dobjc2-nonfragile-abi-impl.m6 @interface Sub1 : Base @end interface
8 @implementation Sub1 @end implementation
Dcategory-super-class-meth.m8 @interface Sub1 : NSObject @end interface
10 @implementation Sub1 implementation
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp246 SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32, in tryInlineAsm() local
250 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in tryInlineAsm()
/external/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp246 SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32, in tryInlineAsm() local
250 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in tryInlineAsm()
/external/clang/test/SemaObjC/
Darc-repeated-weak.mm332 @interface Sub1 : Base1 interface
334 @interface Sub1(cat) interface in cat
338 void test1(Sub1 *s) {
347 void test2(Sub1 *s) {
/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
DBasicValueFactory.h147 inline const llvm::APSInt& Sub1(const llvm::APSInt& V) { in Sub1() function
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelDAGToDAG.cpp586 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in SelectADD_SUB_I64() local
591 DL, MVT::i32, LHS, Sub1); in SelectADD_SUB_I64()
596 DL, MVT::i32, RHS, Sub1); in SelectADD_SUB_I64()
615 Sub1, in SelectADD_SUB_I64()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCCodeEmitter.cpp444 const MCInst *Sub1 = MI.getOperand(1).getInst(); in EncodeSingleInstruction() local
450 unsigned SubBits1 = getBinaryCodeForInstr(*Sub1, Fixups, STI); in EncodeSingleInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelDAGToDAG.cpp706 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in SelectADD_SUB_I64() local
711 DL, MVT::i32, LHS, Sub1); in SelectADD_SUB_I64()
716 DL, MVT::i32, RHS, Sub1); in SelectADD_SUB_I64()
743 Sub1, in SelectADD_SUB_I64()
DAMDGPUISelLowering.cpp1660 SDValue Sub1 = DAG.getBitcast(VT, in LowerUDIVREM64() local
1711 SDValue Rem = DAG.getSelectCC(DL, C3, Zero, Sel2, Sub1, ISD::SETNE); in LowerUDIVREM64()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonConstPropagation.cpp1940 unsigned Sub1 = MI.getOperand(2).getImm(); in evaluate() local
1945 if (Sub1 != SubLo && Sub1 != SubHi) in evaluate()
1949 assert(Sub1 != Sub2); in evaluate()
1950 bool LoIs1 = (Sub1 == SubLo); in evaluate()
DHexagonBitSimplify.cpp439 unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm(); in parseRegSequence() local
445 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence()
446 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence()
451 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence()
/external/llvm/lib/Target/Hexagon/
DHexagonBitSimplify.cpp392 unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm(); in parseRegSequence() local
393 assert(Sub1 != Sub2); in parseRegSequence()
394 if (Sub1 == Hexagon::subreg_loreg && Sub2 == Hexagon::subreg_hireg) { in parseRegSequence()
399 if (Sub1 == Hexagon::subreg_hireg && Sub2 == Hexagon::subreg_loreg) { in parseRegSequence()
/external/googletest/googletest/docs/
Dadvanced.md935 10: void Sub1(int n) {
944 19: Sub1(1);
947 22: Sub1(9);
968 `Sub1()` the two failures come from respectively. (You could add an extra
969 message to each assertion in `Sub1()` to indicate the value of `n`, but that's
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp4272 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32, in tryInlineAsm() local
4276 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in tryInlineAsm()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp4232 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32, in tryInlineAsm() local
4236 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in tryInlineAsm()
/external/antlr/tool/
DCHANGES.txt210 import Sub1, Sub2;