| /external/llvm/lib/Target/ARM/ |
| D | Thumb2ITBlockPass.cpp | 83 for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true); in TrackDefUses() local
84 Subreg.isValid(); ++Subreg) in TrackDefUses()
85 Uses.insert(*Subreg); in TrackDefUses()
90 for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true); in TrackDefUses() local
91 Subreg.isValid(); ++Subreg) in TrackDefUses()
92 Defs.insert(*Subreg); in TrackDefUses()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | Thumb2ITBlockPass.cpp | 100 for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true); in TrackDefUses() local
101 Subreg.isValid(); ++Subreg) in TrackDefUses()
102 Uses.insert(*Subreg); in TrackDefUses()
107 for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true); in TrackDefUses() local
108 Subreg.isValid(); ++Subreg) in TrackDefUses()
109 Defs.insert(*Subreg); in TrackDefUses()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCReduceCRLogicals.cpp | 386 MachineInstr *lookThroughCRCopy(unsigned Reg, unsigned &Subreg,
511 unsigned &Subreg, in lookThroughCRCopy() argument
513 Subreg = -1; in lookThroughCRCopy()
521 Subreg = Copy->getOperand(1).getSubReg(); in lookThroughCRCopy()
526 Subreg = PPC::sub_eq; in lookThroughCRCopy()
528 Subreg = PPC::sub_lt; in lookThroughCRCopy()
530 Subreg = PPC::sub_gt; in lookThroughCRCopy()
532 Subreg = PPC::sub_un; in lookThroughCRCopy()
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2543 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, in Select() local
2548 Subreg, Imm); in Select()
2578 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl, in Select() local
2585 MVT::i32, Subreg, ShiftedImm); in Select()
2603 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, in Select() local
2608 Subreg, Imm); in Select()
2626 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl, in Select() local
2631 Subreg, Imm); in Select()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 2621 unsigned Subreg = (X == 0) ? Hexagon::subreg_loreg : 0; in LowerEXTRACT_VECTOR() local
2624 Subreg = Hexagon::subreg_loreg; in LowerEXTRACT_VECTOR()
2626 Subreg = Hexagon::subreg_hireg; in LowerEXTRACT_VECTOR()
2628 Subreg = Hexagon::subreg_hireg; in LowerEXTRACT_VECTOR()
2630 Subreg = Hexagon::subreg_hireg; in LowerEXTRACT_VECTOR()
2633 N = DAG.getTargetExtractSubreg(Subreg, dl, MVT::i32, Vec); in LowerEXTRACT_VECTOR()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | SelectionDAG.h | 1092 SDValue Operand, SDValue Subreg);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | SelectionDAG.h | 1235 SDValue Operand, SDValue Subreg);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 6178 SDNode *Subreg = getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, in getTargetExtractSubreg() local
6180 return SDValue(Subreg, 0); in getTargetExtractSubreg()
6186 SDValue Operand, SDValue Subreg) { in getTargetInsertSubreg() argument
6189 VT, Operand, Subreg, SRIdxVal); in getTargetInsertSubreg()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 7365 SDNode *Subreg = getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, in getTargetExtractSubreg() local
7367 return SDValue(Subreg, 0); in getTargetExtractSubreg()
7373 SDValue Operand, SDValue Subreg) { in getTargetInsertSubreg() argument
7376 VT, Operand, Subreg, SRIdxVal); in getTargetInsertSubreg()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstrAVX512.td | 1271 RegisterClass SrcRC, SubRegIndex Subreg> {
1282 (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SrcRC:$src, Subreg)))>;
1286 (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SrcRC:$src, Subreg)))>;
1290 (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SrcRC:$src, Subreg)))>;
1295 RegisterClass SrcRC, SubRegIndex Subreg, Predicate prd> {
1298 OpNode, SrcRC, Subreg>, EVEX_V512;
1301 _.info256, OpNode, SrcRC, Subreg>, EVEX_V256;
1303 _.info128, OpNode, SrcRC, Subreg>, EVEX_V128;
|