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Searched refs:Subtarget (Results 1 – 25 of 391) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenFastISel.inc70 …if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
73 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
76 …if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMips…
85 …if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) …
94 …if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
97 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
100 …if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMips…
109 …if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) …
130 if ((Subtarget->inMips16Mode())) {
133 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
[all …]
DMipsGenDAGISel.inc69 … OPC_CheckPatternPredicate, 0, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()…
77 … OPC_CheckPatternPredicate, 1, // (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()…
85 … OPC_CheckPatternPredicate, 2, // (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit(…
93 … 69*/ OPC_CheckPatternPredicate, 3, // (Subtarget->inMicroMipsMode()) && (!Subtarget…
110 …Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isTargetNaCl()) …
117 …Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (…
132 … 135*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarg…
140 /* 150*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
157 …Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isTargetNaCl()) …
164 … OPC_CheckPatternPredicate, 9, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()…
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenFastISel.inc45 if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) {
48 if ((Subtarget->hasSSSE3() && !Subtarget->hasAVX())) {
51 if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) {
60 if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) {
63 if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) {
72 if ((Subtarget->hasBWI())) {
81 if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) {
84 if ((Subtarget->hasSSSE3() && !Subtarget->hasAVX())) {
87 if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) {
96 if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) {
[all …]
/external/llvm/lib/Target/Mips/
DMipsRegisterInfo.cpp98 const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>(); in getCalleeSavedRegs() local
101 if (Subtarget.hasMips64()) in getCalleeSavedRegs()
102 return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList in getCalleeSavedRegs()
105 return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList in getCalleeSavedRegs()
109 if (Subtarget.isSingleFloat()) in getCalleeSavedRegs()
112 if (Subtarget.isABI_N64()) in getCalleeSavedRegs()
115 if (Subtarget.isABI_N32()) in getCalleeSavedRegs()
118 if (Subtarget.isFP64bit()) in getCalleeSavedRegs()
121 if (Subtarget.isFPXX()) in getCalleeSavedRegs()
130 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>(); in getCallPreservedMask() local
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsRegisterInfo.cpp95 const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>(); in getCalleeSavedRegs() local
98 if (Subtarget.hasMips64()) in getCalleeSavedRegs()
99 return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList in getCalleeSavedRegs()
102 return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList in getCalleeSavedRegs()
106 if (Subtarget.isSingleFloat()) in getCalleeSavedRegs()
109 if (Subtarget.isABI_N64()) in getCalleeSavedRegs()
112 if (Subtarget.isABI_N32()) in getCalleeSavedRegs()
115 if (Subtarget.isFP64bit()) in getCalleeSavedRegs()
118 if (Subtarget.isFPXX()) in getCalleeSavedRegs()
127 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>(); in getCallPreservedMask() local
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenFastISel.inc78 if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) {
96 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
99 if ((!Subtarget->isThumb()) && (!Subtarget->hasV4TOps())) {
102 if ((Subtarget->hasV4TOps()) && (!Subtarget->isThumb())) {
120 if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) {
138 if ((Subtarget->isThumb2())) {
141 if ((!Subtarget->isThumb())) {
159 if ((Subtarget->isThumb2())) {
162 if ((!Subtarget->isThumb())) {
180 if ((Subtarget->isThumb2())) {
[all …]
DARMGenDAGISel.inc82 /* 49*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasV6Ops()) && (!Subtarget->isThum…
90 /* 67*/ OPC_CheckPatternPredicate, 1, // (Subtarget->isThumb2())
120 /* 124*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasV6Ops()) && (!Subtarget->isThum…
128 /* 142*/ OPC_CheckPatternPredicate, 1, // (Subtarget->isThumb2())
154 /* 193*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasV6Ops()) && (!Subtarget->isThumb(…
180 /* 248*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasV6Ops()) && (!Subtarget->isThum…
199 /* 287*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasV6Ops()) && (!Subtarget->isThum…
226 /* 342*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasDSP()) && (Subtarget->isThumb2())
253 /* 400*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasDSP()) && (Subtarget->isThumb…
272 /* 439*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasDSP()) && (Subtarget->isThumb…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp137 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); in getCalleeSavedRegs() local
139 if (Subtarget.hasVSX()) in getCalleeSavedRegs()
141 if (Subtarget.hasAltivec()) in getCalleeSavedRegs()
146 if (Subtarget.isDarwinABI()) in getCalleeSavedRegs()
148 ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList in getCalleeSavedRegs()
150 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList in getCalleeSavedRegs()
156 if (Subtarget.hasSPE()) in getCalleeSavedRegs()
164 ? (Subtarget.hasAltivec() in getCalleeSavedRegs()
169 : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_SaveList in getCalleeSavedRegs()
174 ? (Subtarget.hasAltivec() in getCalleeSavedRegs()
[all …]
DPPCFrameLowering.cpp85 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)), in PPCFrameLowering()
86 TOCSaveOffset(computeTOCSaveOffset(Subtarget)), in PPCFrameLowering()
87 FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)), in PPCFrameLowering()
88 LinkageSize(computeLinkageSize(Subtarget)), in PPCFrameLowering()
94 if (Subtarget.isDarwinABI()) { in getCalleeSavedSpillSlots()
96 if (Subtarget.isPPC64()) { in getCalleeSavedSpillSlots()
106 if (!Subtarget.isSVR4ABI()) { in getCalleeSavedSpillSlots()
256 if (Subtarget.isPPC64()) { in getCalleeSavedSpillSlots()
454 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in determineFrameLayout()
465 bool FitsInRedZone = FrameSize <= Subtarget.getRedZoneSize(); in determineFrameLayout()
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp103 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); in getCalleeSavedRegs() local
105 if (Subtarget.hasVSX()) in getCalleeSavedRegs()
107 if (Subtarget.hasAltivec()) in getCalleeSavedRegs()
112 if (Subtarget.isDarwinABI()) in getCalleeSavedRegs()
114 ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList in getCalleeSavedRegs()
116 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList in getCalleeSavedRegs()
126 ? (Subtarget.hasAltivec() in getCalleeSavedRegs()
130 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList in getCalleeSavedRegs()
137 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); in getCalleeSavedRegsViaCopy() local
138 if (Subtarget.isDarwinABI()) in getCalleeSavedRegsViaCopy()
[all …]
DPPCFrameLowering.cpp85 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)), in PPCFrameLowering()
86 TOCSaveOffset(computeTOCSaveOffset(Subtarget)), in PPCFrameLowering()
87 FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)), in PPCFrameLowering()
88 LinkageSize(computeLinkageSize(Subtarget)), in PPCFrameLowering()
94 if (Subtarget.isDarwinABI()) { in getCalleeSavedSpillSlots()
96 if (Subtarget.isPPC64()) { in getCalleeSavedSpillSlots()
106 if (!Subtarget.isSVR4ABI()) { in getCalleeSavedSpillSlots()
236 if (Subtarget.isPPC64()) { in getCalleeSavedSpillSlots()
437 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); in determineFrameLayout()
447 (Subtarget.isPPC64() || // 32-bit SVR4, no stack- in determineFrameLayout()
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenFastISel.inc139 if ((Subtarget->hasNEON())) {
148 if ((Subtarget->hasNEON())) {
157 if ((Subtarget->hasNEON())) {
166 if ((Subtarget->hasNEON())) {
175 if ((Subtarget->hasNEON())) {
184 if ((Subtarget->hasNEON())) {
193 if ((Subtarget->hasNEON())) {
202 if ((Subtarget->hasNEON())) {
227 if ((Subtarget->hasNEON())) {
236 if ((Subtarget->hasNEON())) {
[all …]
DAArch64GenDAGISel.inc814 /* 1610*/ OPC_CheckPatternPredicate, 0, // (Subtarget->isLittleEndian())
990 /* 1982*/ OPC_CheckPatternPredicate, 1, // (!Subtarget->isSTRQroSlow() || MF->getFunction…
1026 /* 2051*/ OPC_CheckPatternPredicate, 0, // (Subtarget->isLittleEndian())
1079 /* 2172*/ OPC_CheckPatternPredicate, 0, // (Subtarget->isLittleEndian())
1114 /* 2240*/ OPC_CheckPatternPredicate, 0, // (Subtarget->isLittleEndian())
1167 /* 2361*/ OPC_CheckPatternPredicate, 0, // (Subtarget->isLittleEndian())
1220 /* 2482*/ OPC_CheckPatternPredicate, 0, // (Subtarget->isLittleEndian())
1271 /* 2584*/ OPC_CheckPatternPredicate, 0, // (Subtarget->isLittleEndian())
1317 /* 2692*/ OPC_CheckPatternPredicate, 0, // (Subtarget->isLittleEndian())
1348 /* 2768*/ OPC_CheckPatternPredicate, 2, // (Subtarget->isLittleEndian()) && (!Subtarget->…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp102 : TargetLowering(TM), Subtarget(STI) { in X86TargetLowering()
103 bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87(); in X86TargetLowering()
104 X86ScalarSSEf64 = Subtarget.hasSSE2(); in X86TargetLowering()
105 X86ScalarSSEf32 = Subtarget.hasSSE1(); in X86TargetLowering()
118 if (Subtarget.isAtom()) in X86TargetLowering()
120 else if (Subtarget.is64Bit()) in X86TargetLowering()
124 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in X86TargetLowering()
129 if (Subtarget.hasSlowDivide32()) in X86TargetLowering()
131 if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit()) in X86TargetLowering()
135 if (Subtarget.isTargetKnownWindowsMSVC() || in X86TargetLowering()
[all …]
DX86RegisterInfo.cpp126 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>(); in getLargestLegalSuperClass() local
135 if (!Subtarget.hasAVX512() && in getLargestLegalSuperClass()
142 if (!Subtarget.hasVLX() && in getLargestLegalSuperClass()
149 if (Subtarget.hasVLX() && in getLargestLegalSuperClass()
156 if (Subtarget.hasAVX512() && in getLargestLegalSuperClass()
181 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>(); in getPointerRegClass() local
185 if (Subtarget.isTarget64BitLP64()) in getPointerRegClass()
201 if (Subtarget.isTarget64BitLP64()) in getPointerRegClass()
206 if (Subtarget.isTarget64BitLP64()) in getPointerRegClass()
210 if (Subtarget.isTarget64BitLP64()) in getPointerRegClass()
[all …]
DX86SelectionDAGInfo.cpp70 const X86Subtarget &Subtarget = in EmitTargetCodeForMemset() local
88 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold()) { in EmitTargetCodeForMemset()
144 if (Subtarget.is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned in EmitTargetCodeForMemset()
173 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX, in EmitTargetCodeForMemset()
176 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RDI : X86::EDI, in EmitTargetCodeForMemset()
210 const X86Subtarget &Subtarget = in EmitTargetCodeForMemcpy() local
215 if (!AlwaysInline && Repeats.Size > Subtarget.getMaxInlineSizeThreshold()) in EmitTargetCodeForMemcpy()
239 if (!Subtarget.hasERMSB() && !(Align & 1)) { in EmitTargetCodeForMemcpy()
248 Repeats.AVT = Subtarget.is64Bit() ? MVT::i64 : MVT::i32; in EmitTargetCodeForMemcpy()
259 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX, in EmitTargetCodeForMemcpy()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPU.td15 // Subtarget Features (device properties)
267 // Subtarget Features (options and debugging)
636 "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
637 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
641 "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
645 "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
650 "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
653 def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
656 def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
658 def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
[all …]
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp74 : TargetLowering(TM), Subtarget(STI) { in X86TargetLowering()
75 bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87(); in X86TargetLowering()
76 X86ScalarSSEf64 = Subtarget.hasSSE2(); in X86TargetLowering()
77 X86ScalarSSEf32 = Subtarget.hasSSE1(); in X86TargetLowering()
90 if (Subtarget.isAtom()) in X86TargetLowering()
92 else if (Subtarget.is64Bit()) in X86TargetLowering()
96 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in X86TargetLowering()
101 if (Subtarget.hasSlowDivide32()) in X86TargetLowering()
103 if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit()) in X86TargetLowering()
107 if (Subtarget.isTargetKnownWindowsMSVC()) { in X86TargetLowering()
[all …]
DX86RegisterInfo.cpp159 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>(); in getPointerRegClass() local
163 if (Subtarget.isTarget64BitLP64()) in getPointerRegClass()
179 if (Subtarget.isTarget64BitLP64()) in getPointerRegClass()
184 if (Subtarget.isTarget64BitLP64()) in getPointerRegClass()
188 if (Subtarget.isTarget64BitLP64()) in getPointerRegClass()
244 const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>(); in getCalleeSavedRegs() local
245 bool HasSSE = Subtarget.hasSSE1(); in getCalleeSavedRegs()
246 bool HasAVX = Subtarget.hasAVX(); in getCalleeSavedRegs()
247 bool HasAVX512 = Subtarget.hasAVX512(); in getCalleeSavedRegs()
320 if (Subtarget.getTargetLowering()->supportSwiftError() && in getCalleeSavedRegs()
[all …]
DX86SelectionDAGInfo.cpp52 const X86Subtarget &Subtarget = in EmitTargetCodeForMemset() local
70 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold()) { in EmitTargetCodeForMemset()
75 V->isNullValue() ? Subtarget.getBZeroEntry() : nullptr) { in EmitTargetCodeForMemset()
124 if (Subtarget.is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned in EmitTargetCodeForMemset()
153 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX, in EmitTargetCodeForMemset()
156 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RDI : X86::EDI, in EmitTargetCodeForMemset()
203 const X86Subtarget &Subtarget = in EmitTargetCodeForMemcpy() local
208 if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold()) in EmitTargetCodeForMemcpy()
239 AVT = Subtarget.is64Bit() ? MVT::i64 : MVT::i32; in EmitTargetCodeForMemcpy()
247 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX, in EmitTargetCodeForMemcpy()
[all …]
/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.cpp57 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getReservedRegs() local
68 if (!Subtarget.is64Bit()) in getReservedRegs()
83 if (ReserveAppRegisters || !Subtarget.is64Bit()) in getReservedRegs()
91 if (!Subtarget.isV9()) { in getReservedRegs()
104 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getPointerRegClass() local
105 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; in getPointerRegClass()
170 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in eliminateFrameIndex() local
179 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { in eliminateFrameIndex()
181 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
193 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcRegisterInfo.cpp57 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getReservedRegs() local
68 if (!Subtarget.is64Bit()) in getReservedRegs()
83 if (ReserveAppRegisters || !Subtarget.is64Bit()) in getReservedRegs()
91 if (!Subtarget.isV9()) { in getReservedRegs()
104 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getPointerRegClass() local
105 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; in getPointerRegClass()
170 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in eliminateFrameIndex() local
179 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { in eliminateFrameIndex()
181 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
193 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCV.td19 def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
25 def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
31 def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
38 def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
44 def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
50 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
52 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/
DBPFTargetMachine.cpp70 Subtarget(TT, CPU, FS, *this) { in BPFTargetMachine()
74 MAI->setDwarfUsesRelocationsAcrossSections(!Subtarget.getUseDwarfRIS()); in BPFTargetMachine()
110 const BPFSubtarget *Subtarget = getBPFTargetMachine().getSubtargetImpl(); in addMachineSSAOptimization() local
111 if (Subtarget->getHasAlu32() && !DisableMIPeephole) in addMachineSSAOptimization()
116 const BPFSubtarget *Subtarget = getBPFTargetMachine().getSubtargetImpl(); in addPreEmitPass() local
119 if (Subtarget->getHasAlu32() && !DisableMIPeephole) in addPreEmitPass()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMISelLowering.cpp225 : TargetLowering(TM), Subtarget(&STI) { in ARMTargetLowering()
226 RegInfo = Subtarget->getRegisterInfo(); in ARMTargetLowering()
227 Itins = Subtarget->getInstrItineraryData(); in ARMTargetLowering()
232 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() && in ARMTargetLowering()
233 !Subtarget->isTargetWatchOS()) { in ARMTargetLowering()
241 if (Subtarget->isTargetMachO()) { in ARMTargetLowering()
243 if (Subtarget->isThumb() && Subtarget->hasVFP2() && in ARMTargetLowering()
244 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) { in ARMTargetLowering()
319 if (Subtarget->isAAPCS_ABI() && in ARMTargetLowering()
320 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() || in ARMTargetLowering()
[all …]

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