1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2011 4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 5 * 6 * Copyright (C) 2009 TechNexion Ltd. 7 */ 8 9 #ifndef __TAM3517_H 10 #define __TAM3517_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 16 #include <asm/arch/cpu.h> /* get chip and board defs */ 17 #include <asm/arch/omap.h> 18 19 /* Clock Defines */ 20 #define V_OSCK 26000000 /* Clock output from T2 */ 21 #define V_SCLK (V_OSCK >> 1) 22 23 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 24 #define CONFIG_SETUP_MEMORY_TAGS 25 #define CONFIG_INITRD_TAG 26 #define CONFIG_REVISION_TAG 27 28 /* 29 * Size of malloc() pool 30 */ 31 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ 32 2 * 1024 * 1024) 33 /* 34 * DDR related 35 */ 36 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 37 38 /* 39 * Hardware drivers 40 */ 41 42 /* 43 * NS16550 Configuration 44 */ 45 #define CONFIG_SYS_NS16550_SERIAL 46 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 47 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 48 49 /* 50 * select serial console configuration 51 */ 52 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 53 54 /* allow to overwrite serial and ethaddr */ 55 #define CONFIG_ENV_OVERWRITE 56 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 57 115200} 58 /* EHCI */ 59 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 60 61 #define CONFIG_SYS_I2C 62 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ 63 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 64 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 65 66 /* 67 * Board NAND Info. 68 */ 69 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 70 /* to access */ 71 /* nand at CS0 */ 72 73 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 74 /* NAND devices */ 75 76 /* 77 * Miscellaneous configurable options 78 */ 79 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 80 81 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 82 /* args */ 83 /* memtest works on */ 84 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 85 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 86 0x01F00000) /* 31MB */ 87 88 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 89 /* address */ 90 91 /* 92 * AM3517 has 12 GP timers, they can be driven by the system clock 93 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 94 * This rate is divided by a local divisor. 95 */ 96 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 97 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 98 99 /* 100 * Physical Memory Map 101 */ 102 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 103 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 104 105 /* 106 * FLASH and environment organization 107 */ 108 109 /* **** PISMO SUPPORT *** */ 110 111 /* Redundant Environment */ 112 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 113 114 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 115 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 116 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 117 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 118 CONFIG_SYS_INIT_RAM_SIZE - \ 119 GENERATED_GBL_DATA_SIZE) 120 121 /* 122 * ethernet support, EMAC 123 * 124 */ 125 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 126 #define CONFIG_BOOTP_DNS2 127 #define CONFIG_BOOTP_SEND_HOSTNAME 128 #define CONFIG_NET_RETRY_COUNT 10 129 130 /* Defines for SPL */ 131 #define CONFIG_SPL_CONSOLE 132 #define CONFIG_SPL_NAND_SOFTECC 133 #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ 134 135 #define CONFIG_SPL_NAND_BASE 136 #define CONFIG_SPL_NAND_DRIVERS 137 #define CONFIG_SPL_NAND_ECC 138 139 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 140 CONFIG_SPL_TEXT_BASE) 141 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 142 143 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 144 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 145 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 146 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 147 148 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 149 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 150 151 /* FAT */ 152 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" 153 #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" 154 155 /* RAW SD card / eMMC */ 156 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ 157 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ 158 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ 159 160 /* NAND boot config */ 161 #define CONFIG_SYS_NAND_PAGE_COUNT 64 162 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 163 #define CONFIG_SYS_NAND_OOBSIZE 64 164 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 165 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 166 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 167 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 168 48, 49, 50, 51, 52, 53, 54, 55,\ 169 56, 57, 58, 59, 60, 61, 62, 63} 170 #define CONFIG_SYS_NAND_ECCSIZE 256 171 #define CONFIG_SYS_NAND_ECCBYTES 3 172 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 173 174 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 175 176 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 177 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 178 179 /* Setup MTD for NAND on the SOM */ 180 181 #define CONFIG_TAM3517_SETTINGS \ 182 "netdev=eth0\0" \ 183 "nandargs=setenv bootargs root=${nandroot} " \ 184 "rootfstype=${nandrootfstype}\0" \ 185 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 186 "nfsroot=${serverip}:${rootpath}\0" \ 187 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 188 "addip_sta=setenv bootargs ${bootargs} " \ 189 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 190 ":${hostname}:${netdev}:off panic=1\0" \ 191 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 192 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 193 "else run addip_sta;fi\0" \ 194 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 195 "addtty=setenv bootargs ${bootargs}" \ 196 " console=ttyO0,${baudrate}\0" \ 197 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 198 "loadaddr=82000000\0" \ 199 "kernel_addr_r=82000000\0" \ 200 "hostname=" CONFIG_HOSTNAME "\0" \ 201 "bootfile=" CONFIG_HOSTNAME "/uImage\0" \ 202 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 203 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 204 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 205 "bootm ${kernel_addr}\0" \ 206 "nandboot=run nandargs addip addtty addmtd addmisc;" \ 207 "nand read ${kernel_addr_r} kernel\0" \ 208 "bootm ${kernel_addr_r}\0" \ 209 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 210 "run nfsargs addip addtty addmtd addmisc;" \ 211 "bootm ${kernel_addr_r}\0" \ 212 "net_self=if run net_self_load;then " \ 213 "run ramargs addip addtty addmtd addmisc;" \ 214 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ 215 "else echo Images not loades;fi\0" \ 216 "u-boot=" CONFIG_HOSTNAME "/u-boot.img\0" \ 217 "load=tftp ${loadaddr} ${u-boot}\0" \ 218 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 219 "mlo=" CONFIG_HOSTNAME "/MLO\0" \ 220 "uboot_addr=0x80000\0" \ 221 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 222 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 223 "updatemlo=nandecc hw;nand erase 0 20000;" \ 224 "nand write ${loadaddr} 0 20000\0" \ 225 "upd=if run load;then echo Updating u-boot;if run update;" \ 226 "then echo U-Boot updated;" \ 227 "else echo Error updating u-boot !;" \ 228 "echo Board without bootloader !!;" \ 229 "fi;" \ 230 "else echo U-Boot not downloaded..exiting;fi\0" \ 231 232 /* 233 * this is common code for all TAM3517 boards. 234 * MAC address is stored from manufacturer in 235 * I2C EEPROM 236 */ 237 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 238 /* 239 * The I2C EEPROM on the TAM3517 contains 240 * mac address and production data 241 */ 242 struct tam3517_module_info { 243 char customer[48]; 244 char product[48]; 245 246 /* 247 * bit 0~47 : sequence number 248 * bit 48~55 : week of year, from 0. 249 * bit 56~63 : year 250 */ 251 unsigned long long sequence_number; 252 253 /* 254 * bit 0~7 : revision fixed 255 * bit 8~15 : revision major 256 * bit 16~31 : TNxxx 257 */ 258 unsigned int revision; 259 unsigned char eth_addr[4][8]; 260 unsigned char _rev[100]; 261 }; 262 263 #define TAM3517_READ_EEPROM(info, ret) \ 264 do { \ 265 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ 266 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ 267 (void *)info, sizeof(*info))) \ 268 ret = 1; \ 269 else \ 270 ret = 0; \ 271 } while (0) 272 273 #define TAM3517_READ_MAC_FROM_EEPROM(info) \ 274 do { \ 275 char buf[80], ethname[20]; \ 276 int i; \ 277 memset(buf, 0, sizeof(buf)); \ 278 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ 279 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ 280 (info)->eth_addr[i][5], \ 281 (info)->eth_addr[i][4], \ 282 (info)->eth_addr[i][3], \ 283 (info)->eth_addr[i][2], \ 284 (info)->eth_addr[i][1], \ 285 (info)->eth_addr[i][0]); \ 286 \ 287 if (i) \ 288 sprintf(ethname, "eth%daddr", i); \ 289 else \ 290 strcpy(ethname, "ethaddr"); \ 291 printf("Setting %s from EEPROM with %s\n", ethname, buf);\ 292 env_set(ethname, buf); \ 293 } \ 294 } while (0) 295 296 /* The following macros are taken from Technexion's documentation */ 297 #define TAM3517_sequence_number(info) \ 298 ((info)->sequence_number % 0x1000000000000LL) 299 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) 300 #define TAM3517_year(info) ((info)->sequence_number >> 56) 301 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100) 302 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) 303 #define TAM3517_revision_tn(info) ((info)->revision >> 16) 304 305 #define TAM3517_PRINT_SOM_INFO(info) \ 306 do { \ 307 printf("Vendor:%s\n", (info)->customer); \ 308 printf("SOM: %s\n", (info)->product); \ 309 printf("SeqNr: %02llu%02llu%012llu\n", \ 310 TAM3517_year(info), \ 311 TAM3517_week_of_year(info), \ 312 TAM3517_sequence_number(info)); \ 313 printf("Rev: TN%u %u.%u\n", \ 314 TAM3517_revision_tn(info), \ 315 TAM3517_revision_major(info), \ 316 TAM3517_revision_fixed(info)); \ 317 } while (0) 318 319 #endif 320 321 #endif /* __TAM3517_H */ 322