1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * rtl8169.c : U-Boot driver for the RealTek RTL8169
4 *
5 * Masami Komiya (mkomiya@sonare.it)
6 *
7 * Most part is taken from r8169.c of etherboot
8 *
9 */
10
11 /**************************************************************************
12 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
13 * Written 2003 by Timothy Legge <tlegge@rogers.com>
14 *
15 * Portions of this code based on:
16 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
17 * for Linux kernel 2.4.x.
18 *
19 * Written 2002 ShuChen <shuchen@realtek.com.tw>
20 * See Linux Driver for full information
21 *
22 * Linux Driver Version 1.27a, 10.02.2002
23 *
24 * Thanks to:
25 * Jean Chen of RealTek Semiconductor Corp. for
26 * providing the evaluation NIC used to develop
27 * this driver. RealTek's support for Etherboot
28 * is appreciated.
29 *
30 * REVISION HISTORY:
31 * ================
32 *
33 * v1.0 11-26-2003 timlegge Initial port of Linux driver
34 * v1.5 01-17-2004 timlegge Initial driver output cleanup
35 *
36 * Indent Options: indent -kr -i8
37 ***************************************************************************/
38 /*
39 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
40 * Modified to use le32_to_cpu and cpu_to_le32 properly
41 */
42 #include <common.h>
43 #include <cpu_func.h>
44 #include <dm.h>
45 #include <errno.h>
46 #include <malloc.h>
47 #include <memalign.h>
48 #include <net.h>
49 #ifndef CONFIG_DM_ETH
50 #include <netdev.h>
51 #endif
52 #include <asm/io.h>
53 #include <pci.h>
54
55 #undef DEBUG_RTL8169
56 #undef DEBUG_RTL8169_TX
57 #undef DEBUG_RTL8169_RX
58
59 #define drv_version "v1.5"
60 #define drv_date "01-17-2004"
61
62 static unsigned long ioaddr;
63
64 /* Condensed operations for readability. */
65 #define currticks() get_timer(0)
66
67 /* media options */
68 #define MAX_UNITS 8
69 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
70
71 /* MAC address length*/
72 #define MAC_ADDR_LEN 6
73
74 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
75 #define MAX_ETH_FRAME_SIZE 1536
76
77 #define TX_FIFO_THRESH 256 /* In bytes */
78
79 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
80 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
81 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
82 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
83 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
84 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
85
86 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
87 #ifdef CONFIG_SYS_RX_ETH_BUFFER
88 #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER
89 #else
90 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
91 #endif
92 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
93 #define RX_BUF_LEN 8192
94
95 #define RTL_MIN_IO_SIZE 0x80
96 #define TX_TIMEOUT (6*HZ)
97
98 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
99 #define RTL_W8(reg, val8) writeb((val8), ioaddr + (reg))
100 #define RTL_W16(reg, val16) writew((val16), ioaddr + (reg))
101 #define RTL_W32(reg, val32) writel((val32), ioaddr + (reg))
102 #define RTL_R8(reg) readb(ioaddr + (reg))
103 #define RTL_R16(reg) readw(ioaddr + (reg))
104 #define RTL_R32(reg) readl(ioaddr + (reg))
105
106 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \
107 (pci_addr_t)(unsigned long)a)
108 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \
109 (phys_addr_t)a)
110
111 enum RTL8169_registers {
112 MAC0 = 0, /* Ethernet hardware address. */
113 MAR0 = 8, /* Multicast filter. */
114 TxDescStartAddrLow = 0x20,
115 TxDescStartAddrHigh = 0x24,
116 TxHDescStartAddrLow = 0x28,
117 TxHDescStartAddrHigh = 0x2c,
118 FLASH = 0x30,
119 ERSR = 0x36,
120 ChipCmd = 0x37,
121 TxPoll = 0x38,
122 IntrMask = 0x3C,
123 IntrStatus = 0x3E,
124 TxConfig = 0x40,
125 RxConfig = 0x44,
126 RxMissed = 0x4C,
127 Cfg9346 = 0x50,
128 Config0 = 0x51,
129 Config1 = 0x52,
130 Config2 = 0x53,
131 Config3 = 0x54,
132 Config4 = 0x55,
133 Config5 = 0x56,
134 MultiIntr = 0x5C,
135 PHYAR = 0x60,
136 TBICSR = 0x64,
137 TBI_ANAR = 0x68,
138 TBI_LPAR = 0x6A,
139 PHYstatus = 0x6C,
140 RxMaxSize = 0xDA,
141 CPlusCmd = 0xE0,
142 RxDescStartAddrLow = 0xE4,
143 RxDescStartAddrHigh = 0xE8,
144 EarlyTxThres = 0xEC,
145 FuncEvent = 0xF0,
146 FuncEventMask = 0xF4,
147 FuncPresetState = 0xF8,
148 FuncForceEvent = 0xFC,
149 };
150
151 enum RTL8169_register_content {
152 /*InterruptStatusBits */
153 SYSErr = 0x8000,
154 PCSTimeout = 0x4000,
155 SWInt = 0x0100,
156 TxDescUnavail = 0x80,
157 RxFIFOOver = 0x40,
158 RxUnderrun = 0x20,
159 RxOverflow = 0x10,
160 TxErr = 0x08,
161 TxOK = 0x04,
162 RxErr = 0x02,
163 RxOK = 0x01,
164
165 /*RxStatusDesc */
166 RxRES = 0x00200000,
167 RxCRC = 0x00080000,
168 RxRUNT = 0x00100000,
169 RxRWT = 0x00400000,
170
171 /*ChipCmdBits */
172 CmdReset = 0x10,
173 CmdRxEnb = 0x08,
174 CmdTxEnb = 0x04,
175 RxBufEmpty = 0x01,
176
177 /*Cfg9346Bits */
178 Cfg9346_Lock = 0x00,
179 Cfg9346_Unlock = 0xC0,
180
181 /*rx_mode_bits */
182 AcceptErr = 0x20,
183 AcceptRunt = 0x10,
184 AcceptBroadcast = 0x08,
185 AcceptMulticast = 0x04,
186 AcceptMyPhys = 0x02,
187 AcceptAllPhys = 0x01,
188
189 /*RxConfigBits */
190 RxCfgFIFOShift = 13,
191 RxCfgDMAShift = 8,
192
193 /*TxConfigBits */
194 TxInterFrameGapShift = 24,
195 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
196
197 /*rtl8169_PHYstatus */
198 TBI_Enable = 0x80,
199 TxFlowCtrl = 0x40,
200 RxFlowCtrl = 0x20,
201 _1000bpsF = 0x10,
202 _100bps = 0x08,
203 _10bps = 0x04,
204 LinkStatus = 0x02,
205 FullDup = 0x01,
206
207 /*GIGABIT_PHY_registers */
208 PHY_CTRL_REG = 0,
209 PHY_STAT_REG = 1,
210 PHY_AUTO_NEGO_REG = 4,
211 PHY_1000_CTRL_REG = 9,
212
213 /*GIGABIT_PHY_REG_BIT */
214 PHY_Restart_Auto_Nego = 0x0200,
215 PHY_Enable_Auto_Nego = 0x1000,
216
217 /* PHY_STAT_REG = 1; */
218 PHY_Auto_Nego_Comp = 0x0020,
219
220 /* PHY_AUTO_NEGO_REG = 4; */
221 PHY_Cap_10_Half = 0x0020,
222 PHY_Cap_10_Full = 0x0040,
223 PHY_Cap_100_Half = 0x0080,
224 PHY_Cap_100_Full = 0x0100,
225
226 /* PHY_1000_CTRL_REG = 9; */
227 PHY_Cap_1000_Full = 0x0200,
228
229 PHY_Cap_Null = 0x0,
230
231 /*_MediaType*/
232 _10_Half = 0x01,
233 _10_Full = 0x02,
234 _100_Half = 0x04,
235 _100_Full = 0x08,
236 _1000_Full = 0x10,
237
238 /*_TBICSRBit*/
239 TBILinkOK = 0x02000000,
240 };
241
242 static struct {
243 const char *name;
244 u8 version; /* depend on RTL8169 docs */
245 u32 RxConfigMask; /* should clear the bits supported by this chip */
246 } rtl_chip_info[] = {
247 {"RTL-8169", 0x00, 0xff7e1880,},
248 {"RTL-8169", 0x04, 0xff7e1880,},
249 {"RTL-8169", 0x00, 0xff7e1880,},
250 {"RTL-8169s/8110s", 0x02, 0xff7e1880,},
251 {"RTL-8169s/8110s", 0x04, 0xff7e1880,},
252 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,},
253 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,},
254 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,},
255 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,},
256 {"RTL-8168c/8111c", 0x3c, 0xff7e1880,},
257 {"RTL-8168d/8111d", 0x28, 0xff7e1880,},
258 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,},
259 {"RTL-8168/8111g", 0x4c, 0xff7e1880,},
260 {"RTL-8101e", 0x34, 0xff7e1880,},
261 {"RTL-8100e", 0x32, 0xff7e1880,},
262 {"RTL-8168h/8111h", 0x54, 0xff7e1880,},
263 };
264
265 enum _DescStatusBit {
266 OWNbit = 0x80000000,
267 EORbit = 0x40000000,
268 FSbit = 0x20000000,
269 LSbit = 0x10000000,
270 };
271
272 struct TxDesc {
273 u32 status;
274 u32 vlan_tag;
275 u32 buf_addr;
276 u32 buf_Haddr;
277 };
278
279 struct RxDesc {
280 u32 status;
281 u32 vlan_tag;
282 u32 buf_addr;
283 u32 buf_Haddr;
284 };
285
286 static unsigned char rxdata[RX_BUF_LEN];
287
288 #define RTL8169_DESC_SIZE 16
289
290 #if ARCH_DMA_MINALIGN > 256
291 # define RTL8169_ALIGN ARCH_DMA_MINALIGN
292 #else
293 # define RTL8169_ALIGN 256
294 #endif
295
296 /*
297 * Warn if the cache-line size is larger than the descriptor size. In such
298 * cases the driver will likely fail because the CPU needs to flush the cache
299 * when requeuing RX buffers, therefore descriptors written by the hardware
300 * may be discarded.
301 *
302 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
303 * the driver to allocate descriptors from a pool of non-cached memory.
304 */
305 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
306 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
307 !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
308 #warning cache-line size is larger than descriptor size
309 #endif
310 #endif
311
312 /*
313 * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All
314 * descriptors point to a part of this buffer.
315 */
316 DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
317
318 /*
319 * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All
320 * descriptors point to a part of this buffer.
321 */
322 DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
323
324 struct rtl8169_private {
325 ulong iobase;
326 void *mmio_addr; /* memory map physical address */
327 int chipset;
328 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
329 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
330 unsigned long dirty_tx;
331 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
332 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
333 unsigned char *RxBufferRings; /* Index of Rx Buffer */
334 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */
335 unsigned char *Tx_skbuff[NUM_TX_DESC];
336 } tpx;
337
338 static struct rtl8169_private *tpc;
339
340 static const unsigned int rtl8169_rx_config =
341 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
342
343 static struct pci_device_id supported[] = {
344 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) },
345 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) },
346 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) },
347 {}
348 };
349
mdio_write(int RegAddr,int value)350 void mdio_write(int RegAddr, int value)
351 {
352 int i;
353
354 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
355 udelay(1000);
356
357 for (i = 2000; i > 0; i--) {
358 /* Check if the RTL8169 has completed writing to the specified MII register */
359 if (!(RTL_R32(PHYAR) & 0x80000000)) {
360 break;
361 } else {
362 udelay(100);
363 }
364 }
365 }
366
mdio_read(int RegAddr)367 int mdio_read(int RegAddr)
368 {
369 int i, value = -1;
370
371 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
372 udelay(1000);
373
374 for (i = 2000; i > 0; i--) {
375 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
376 if (RTL_R32(PHYAR) & 0x80000000) {
377 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
378 break;
379 } else {
380 udelay(100);
381 }
382 }
383 return value;
384 }
385
rtl8169_init_board(unsigned long dev_iobase,const char * name)386 static int rtl8169_init_board(unsigned long dev_iobase, const char *name)
387 {
388 int i;
389 u32 tmp;
390
391 #ifdef DEBUG_RTL8169
392 printf ("%s\n", __FUNCTION__);
393 #endif
394 ioaddr = dev_iobase;
395
396 /* Soft reset the chip. */
397 RTL_W8(ChipCmd, CmdReset);
398
399 /* Check that the chip has finished the reset. */
400 for (i = 1000; i > 0; i--)
401 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
402 break;
403 else
404 udelay(10);
405
406 /* identify chip attached to board */
407 tmp = RTL_R32(TxConfig);
408 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
409
410 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
411 if (tmp == rtl_chip_info[i].version) {
412 tpc->chipset = i;
413 goto match;
414 }
415 }
416
417 /* if unknown chip, assume array element #0, original RTL-8169 in this case */
418 printf("PCI device %s: unknown chip version, assuming RTL-8169\n",
419 name);
420 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
421 tpc->chipset = 0;
422
423 match:
424 return 0;
425 }
426
427 /*
428 * TX and RX descriptors are 16 bytes. This causes problems with the cache
429 * maintenance on CPUs where the cache-line size exceeds the size of these
430 * descriptors. What will happen is that when the driver receives a packet
431 * it will be immediately requeued for the hardware to reuse. The CPU will
432 * therefore need to flush the cache-line containing the descriptor, which
433 * will cause all other descriptors in the same cache-line to be flushed
434 * along with it. If one of those descriptors had been written to by the
435 * device those changes (and the associated packet) will be lost.
436 *
437 * To work around this, we make use of non-cached memory if available. If
438 * descriptors are mapped uncached there's no need to manually flush them
439 * or invalidate them.
440 *
441 * Note that this only applies to descriptors. The packet data buffers do
442 * not have the same constraints since they are 1536 bytes large, so they
443 * are unlikely to share cache-lines.
444 */
rtl_alloc_descs(unsigned int num)445 static void *rtl_alloc_descs(unsigned int num)
446 {
447 size_t size = num * RTL8169_DESC_SIZE;
448
449 #ifdef CONFIG_SYS_NONCACHED_MEMORY
450 return (void *)noncached_alloc(size, RTL8169_ALIGN);
451 #else
452 return memalign(RTL8169_ALIGN, size);
453 #endif
454 }
455
456 /*
457 * Cache maintenance functions. These are simple wrappers around the more
458 * general purpose flush_cache() and invalidate_dcache_range() functions.
459 */
460
rtl_inval_rx_desc(struct RxDesc * desc)461 static void rtl_inval_rx_desc(struct RxDesc *desc)
462 {
463 #ifndef CONFIG_SYS_NONCACHED_MEMORY
464 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
465 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
466
467 invalidate_dcache_range(start, end);
468 #endif
469 }
470
rtl_flush_rx_desc(struct RxDesc * desc)471 static void rtl_flush_rx_desc(struct RxDesc *desc)
472 {
473 #ifndef CONFIG_SYS_NONCACHED_MEMORY
474 flush_cache((unsigned long)desc, sizeof(*desc));
475 #endif
476 }
477
rtl_inval_tx_desc(struct TxDesc * desc)478 static void rtl_inval_tx_desc(struct TxDesc *desc)
479 {
480 #ifndef CONFIG_SYS_NONCACHED_MEMORY
481 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
482 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
483
484 invalidate_dcache_range(start, end);
485 #endif
486 }
487
rtl_flush_tx_desc(struct TxDesc * desc)488 static void rtl_flush_tx_desc(struct TxDesc *desc)
489 {
490 #ifndef CONFIG_SYS_NONCACHED_MEMORY
491 flush_cache((unsigned long)desc, sizeof(*desc));
492 #endif
493 }
494
rtl_inval_buffer(void * buf,size_t size)495 static void rtl_inval_buffer(void *buf, size_t size)
496 {
497 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
498 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
499
500 invalidate_dcache_range(start, end);
501 }
502
rtl_flush_buffer(void * buf,size_t size)503 static void rtl_flush_buffer(void *buf, size_t size)
504 {
505 flush_cache((unsigned long)buf, size);
506 }
507
508 /**************************************************************************
509 RECV - Receive a frame
510 ***************************************************************************/
511 #ifdef CONFIG_DM_ETH
rtl_recv_common(struct udevice * dev,unsigned long dev_iobase,uchar ** packetp)512 static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase,
513 uchar **packetp)
514 #else
515 static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase,
516 uchar **packetp)
517 #endif
518 {
519 /* return true if there's an ethernet packet ready to read */
520 /* nic->packet should contain data on return */
521 /* nic->packetlen should contain length of data */
522 int cur_rx;
523 int length = 0;
524
525 #ifdef DEBUG_RTL8169_RX
526 printf ("%s\n", __FUNCTION__);
527 #endif
528 ioaddr = dev_iobase;
529
530 cur_rx = tpc->cur_rx;
531
532 rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]);
533
534 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
535 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
536 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
537 status) & 0x00001FFF) - 4;
538
539 rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length);
540 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
541
542 if (cur_rx == NUM_RX_DESC - 1)
543 tpc->RxDescArray[cur_rx].status =
544 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
545 else
546 tpc->RxDescArray[cur_rx].status =
547 cpu_to_le32(OWNbit + RX_BUF_SIZE);
548 #ifdef CONFIG_DM_ETH
549 tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
550 dm_pci_mem_to_phys(dev,
551 (pci_addr_t)(unsigned long)
552 tpc->RxBufferRing[cur_rx]));
553 #else
554 tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
555 pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)
556 tpc->RxBufferRing[cur_rx]));
557 #endif
558 rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
559 #ifdef CONFIG_DM_ETH
560 *packetp = rxdata;
561 #else
562 net_process_received_packet(rxdata, length);
563 #endif
564 } else {
565 puts("Error Rx");
566 length = -EIO;
567 }
568 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
569 tpc->cur_rx = cur_rx;
570 return length;
571
572 } else {
573 ushort sts = RTL_R8(IntrStatus);
574 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
575 udelay(100); /* wait */
576 }
577 tpc->cur_rx = cur_rx;
578 return (0); /* initially as this is called to flush the input */
579 }
580
581 #ifdef CONFIG_DM_ETH
rtl8169_eth_recv(struct udevice * dev,int flags,uchar ** packetp)582 int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp)
583 {
584 struct rtl8169_private *priv = dev_get_priv(dev);
585
586 return rtl_recv_common(dev, priv->iobase, packetp);
587 }
588 #else
rtl_recv(struct eth_device * dev)589 static int rtl_recv(struct eth_device *dev)
590 {
591 return rtl_recv_common((pci_dev_t)(unsigned long)dev->priv,
592 dev->iobase, NULL);
593 }
594 #endif /* nCONFIG_DM_ETH */
595
596 #define HZ 1000
597 /**************************************************************************
598 SEND - Transmit a frame
599 ***************************************************************************/
600 #ifdef CONFIG_DM_ETH
rtl_send_common(struct udevice * dev,unsigned long dev_iobase,void * packet,int length)601 static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase,
602 void *packet, int length)
603 #else
604 static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
605 void *packet, int length)
606 #endif
607 {
608 /* send the packet to destination */
609
610 u32 to;
611 u8 *ptxb;
612 int entry = tpc->cur_tx % NUM_TX_DESC;
613 u32 len = length;
614 int ret;
615
616 #ifdef DEBUG_RTL8169_TX
617 int stime = currticks();
618 printf ("%s\n", __FUNCTION__);
619 printf("sending %d bytes\n", len);
620 #endif
621
622 ioaddr = dev_iobase;
623
624 /* point to the current txb incase multiple tx_rings are used */
625 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
626 memcpy(ptxb, (char *)packet, (int)length);
627
628 while (len < ETH_ZLEN)
629 ptxb[len++] = '\0';
630
631 rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN));
632
633 tpc->TxDescArray[entry].buf_Haddr = 0;
634 #ifdef CONFIG_DM_ETH
635 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
636 dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
637 #else
638 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
639 pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
640 #endif
641 if (entry != (NUM_TX_DESC - 1)) {
642 tpc->TxDescArray[entry].status =
643 cpu_to_le32((OWNbit | FSbit | LSbit) |
644 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
645 } else {
646 tpc->TxDescArray[entry].status =
647 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
648 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
649 }
650 rtl_flush_tx_desc(&tpc->TxDescArray[entry]);
651 RTL_W8(TxPoll, 0x40); /* set polling bit */
652
653 tpc->cur_tx++;
654 to = currticks() + TX_TIMEOUT;
655 do {
656 rtl_inval_tx_desc(&tpc->TxDescArray[entry]);
657 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
658 && (currticks() < to)); /* wait */
659
660 if (currticks() >= to) {
661 #ifdef DEBUG_RTL8169_TX
662 puts("tx timeout/error\n");
663 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
664 #endif
665 ret = -ETIMEDOUT;
666 } else {
667 #ifdef DEBUG_RTL8169_TX
668 puts("tx done\n");
669 #endif
670 ret = 0;
671 }
672 /* Delay to make net console (nc) work properly */
673 udelay(20);
674 return ret;
675 }
676
677 #ifdef CONFIG_DM_ETH
rtl8169_eth_send(struct udevice * dev,void * packet,int length)678 int rtl8169_eth_send(struct udevice *dev, void *packet, int length)
679 {
680 struct rtl8169_private *priv = dev_get_priv(dev);
681
682 return rtl_send_common(dev, priv->iobase, packet, length);
683 }
684
685 #else
rtl_send(struct eth_device * dev,void * packet,int length)686 static int rtl_send(struct eth_device *dev, void *packet, int length)
687 {
688 return rtl_send_common((pci_dev_t)(unsigned long)dev->priv,
689 dev->iobase, packet, length);
690 }
691 #endif
692
rtl8169_set_rx_mode(void)693 static void rtl8169_set_rx_mode(void)
694 {
695 u32 mc_filter[2]; /* Multicast hash filter */
696 int rx_mode;
697 u32 tmp = 0;
698
699 #ifdef DEBUG_RTL8169
700 printf ("%s\n", __FUNCTION__);
701 #endif
702
703 /* IFF_ALLMULTI */
704 /* Too many to filter perfectly -- accept all multicasts. */
705 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
706 mc_filter[1] = mc_filter[0] = 0xffffffff;
707
708 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
709 rtl_chip_info[tpc->chipset].RxConfigMask);
710
711 RTL_W32(RxConfig, tmp);
712 RTL_W32(MAR0 + 0, mc_filter[0]);
713 RTL_W32(MAR0 + 4, mc_filter[1]);
714 }
715
716 #ifdef CONFIG_DM_ETH
rtl8169_hw_start(struct udevice * dev)717 static void rtl8169_hw_start(struct udevice *dev)
718 #else
719 static void rtl8169_hw_start(pci_dev_t dev)
720 #endif
721 {
722 u32 i;
723
724 #ifdef DEBUG_RTL8169
725 int stime = currticks();
726 printf ("%s\n", __FUNCTION__);
727 #endif
728
729 #if 0
730 /* Soft reset the chip. */
731 RTL_W8(ChipCmd, CmdReset);
732
733 /* Check that the chip has finished the reset. */
734 for (i = 1000; i > 0; i--) {
735 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
736 break;
737 else
738 udelay(10);
739 }
740 #endif
741
742 RTL_W8(Cfg9346, Cfg9346_Unlock);
743
744 /* RTL-8169sb/8110sb or previous version */
745 if (tpc->chipset <= 5)
746 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
747
748 RTL_W8(EarlyTxThres, EarlyTxThld);
749
750 /* For gigabit rtl8169 */
751 RTL_W16(RxMaxSize, RxPacketMaxSize);
752
753 /* Set Rx Config register */
754 i = rtl8169_rx_config | (RTL_R32(RxConfig) &
755 rtl_chip_info[tpc->chipset].RxConfigMask);
756 RTL_W32(RxConfig, i);
757
758 /* Set DMA burst size and Interframe Gap Time */
759 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
760 (InterFrameGap << TxInterFrameGapShift));
761
762
763 tpc->cur_rx = 0;
764
765 #ifdef CONFIG_DM_ETH
766 RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev,
767 (pci_addr_t)(unsigned long)tpc->TxDescArray));
768 #else
769 RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev,
770 (pci_addr_t)(unsigned long)tpc->TxDescArray));
771 #endif
772 RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
773 #ifdef CONFIG_DM_ETH
774 RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys(
775 dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
776 #else
777 RTL_W32(RxDescStartAddrLow, pci_mem_to_phys(
778 dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
779 #endif
780 RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
781
782 /* RTL-8169sc/8110sc or later version */
783 if (tpc->chipset > 5)
784 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
785
786 RTL_W8(Cfg9346, Cfg9346_Lock);
787 udelay(10);
788
789 RTL_W32(RxMissed, 0);
790
791 rtl8169_set_rx_mode();
792
793 /* no early-rx interrupts */
794 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
795
796 #ifdef DEBUG_RTL8169
797 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
798 #endif
799 }
800
801 #ifdef CONFIG_DM_ETH
rtl8169_init_ring(struct udevice * dev)802 static void rtl8169_init_ring(struct udevice *dev)
803 #else
804 static void rtl8169_init_ring(pci_dev_t dev)
805 #endif
806 {
807 int i;
808
809 #ifdef DEBUG_RTL8169
810 int stime = currticks();
811 printf ("%s\n", __FUNCTION__);
812 #endif
813
814 tpc->cur_rx = 0;
815 tpc->cur_tx = 0;
816 tpc->dirty_tx = 0;
817 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
818 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
819
820 for (i = 0; i < NUM_TX_DESC; i++) {
821 tpc->Tx_skbuff[i] = &txb[i];
822 }
823
824 for (i = 0; i < NUM_RX_DESC; i++) {
825 if (i == (NUM_RX_DESC - 1))
826 tpc->RxDescArray[i].status =
827 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
828 else
829 tpc->RxDescArray[i].status =
830 cpu_to_le32(OWNbit + RX_BUF_SIZE);
831
832 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
833 #ifdef CONFIG_DM_ETH
834 tpc->RxDescArray[i].buf_addr = cpu_to_le32(dm_pci_mem_to_phys(
835 dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
836 #else
837 tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys(
838 dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
839 #endif
840 rtl_flush_rx_desc(&tpc->RxDescArray[i]);
841 }
842
843 #ifdef DEBUG_RTL8169
844 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
845 #endif
846 }
847
848 #ifdef CONFIG_DM_ETH
rtl8169_common_start(struct udevice * dev,unsigned char * enetaddr,unsigned long dev_iobase)849 static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr,
850 unsigned long dev_iobase)
851 #else
852 static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr,
853 unsigned long dev_iobase)
854 #endif
855 {
856 int i;
857
858 #ifdef DEBUG_RTL8169
859 int stime = currticks();
860 printf ("%s\n", __FUNCTION__);
861 #endif
862
863 ioaddr = dev_iobase;
864
865 rtl8169_init_ring(dev);
866 rtl8169_hw_start(dev);
867 /* Construct a perfect filter frame with the mac address as first match
868 * and broadcast for all others */
869 for (i = 0; i < 192; i++)
870 txb[i] = 0xFF;
871
872 txb[0] = enetaddr[0];
873 txb[1] = enetaddr[1];
874 txb[2] = enetaddr[2];
875 txb[3] = enetaddr[3];
876 txb[4] = enetaddr[4];
877 txb[5] = enetaddr[5];
878
879 #ifdef DEBUG_RTL8169
880 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
881 #endif
882 }
883
884 #ifdef CONFIG_DM_ETH
rtl8169_eth_start(struct udevice * dev)885 static int rtl8169_eth_start(struct udevice *dev)
886 {
887 struct eth_pdata *plat = dev_get_platdata(dev);
888 struct rtl8169_private *priv = dev_get_priv(dev);
889
890 rtl8169_common_start(dev, plat->enetaddr, priv->iobase);
891
892 return 0;
893 }
894 #else
895 /**************************************************************************
896 RESET - Finish setting up the ethernet interface
897 ***************************************************************************/
rtl_reset(struct eth_device * dev,bd_t * bis)898 static int rtl_reset(struct eth_device *dev, bd_t *bis)
899 {
900 rtl8169_common_start((pci_dev_t)(unsigned long)dev->priv,
901 dev->enetaddr, dev->iobase);
902
903 return 0;
904 }
905 #endif /* nCONFIG_DM_ETH */
906
rtl_halt_common(unsigned long dev_iobase)907 static void rtl_halt_common(unsigned long dev_iobase)
908 {
909 int i;
910
911 #ifdef DEBUG_RTL8169
912 printf ("%s\n", __FUNCTION__);
913 #endif
914
915 ioaddr = dev_iobase;
916
917 /* Stop the chip's Tx and Rx DMA processes. */
918 RTL_W8(ChipCmd, 0x00);
919
920 /* Disable interrupts by clearing the interrupt mask. */
921 RTL_W16(IntrMask, 0x0000);
922
923 RTL_W32(RxMissed, 0);
924
925 for (i = 0; i < NUM_RX_DESC; i++) {
926 tpc->RxBufferRing[i] = NULL;
927 }
928 }
929
930 #ifdef CONFIG_DM_ETH
rtl8169_eth_stop(struct udevice * dev)931 void rtl8169_eth_stop(struct udevice *dev)
932 {
933 struct rtl8169_private *priv = dev_get_priv(dev);
934
935 rtl_halt_common(priv->iobase);
936 }
937 #else
938 /**************************************************************************
939 HALT - Turn off ethernet interface
940 ***************************************************************************/
rtl_halt(struct eth_device * dev)941 static void rtl_halt(struct eth_device *dev)
942 {
943 rtl_halt_common(dev->iobase);
944 }
945 #endif
946
947 #ifdef CONFIG_DM_ETH
rtl8169_write_hwaddr(struct udevice * dev)948 static int rtl8169_write_hwaddr(struct udevice *dev)
949 {
950 struct eth_pdata *plat = dev_get_platdata(dev);
951 unsigned int i;
952
953 RTL_W8(Cfg9346, Cfg9346_Unlock);
954
955 for (i = 0; i < MAC_ADDR_LEN; i++)
956 RTL_W8(MAC0 + i, plat->enetaddr[i]);
957
958 RTL_W8(Cfg9346, Cfg9346_Lock);
959
960 return 0;
961 }
962 #endif
963
964 /**************************************************************************
965 INIT - Look for an adapter, this routine's visible to the outside
966 ***************************************************************************/
967
968 #define board_found 1
969 #define valid_link 0
rtl_init(unsigned long dev_ioaddr,const char * name,unsigned char * enetaddr)970 static int rtl_init(unsigned long dev_ioaddr, const char *name,
971 unsigned char *enetaddr)
972 {
973 static int board_idx = -1;
974 int i, rc;
975 int option = -1, Cap10_100 = 0, Cap1000 = 0;
976
977 #ifdef DEBUG_RTL8169
978 printf ("%s\n", __FUNCTION__);
979 #endif
980 ioaddr = dev_ioaddr;
981
982 board_idx++;
983
984 /* point to private storage */
985 tpc = &tpx;
986
987 rc = rtl8169_init_board(ioaddr, name);
988 if (rc)
989 return rc;
990
991 /* Get MAC address. FIXME: read EEPROM */
992 for (i = 0; i < MAC_ADDR_LEN; i++)
993 enetaddr[i] = RTL_R8(MAC0 + i);
994
995 #ifdef DEBUG_RTL8169
996 printf("chipset = %d\n", tpc->chipset);
997 printf("MAC Address");
998 for (i = 0; i < MAC_ADDR_LEN; i++)
999 printf(":%02x", enetaddr[i]);
1000 putc('\n');
1001 #endif
1002
1003 #ifdef DEBUG_RTL8169
1004 /* Print out some hardware info */
1005 printf("%s: at ioaddr 0x%lx\n", name, ioaddr);
1006 #endif
1007
1008 /* if TBI is not endbled */
1009 if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
1010 int val = mdio_read(PHY_AUTO_NEGO_REG);
1011
1012 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1013 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
1014 if (option > 0) {
1015 #ifdef DEBUG_RTL8169
1016 printf("%s: Force-mode Enabled.\n", name);
1017 #endif
1018 Cap10_100 = 0, Cap1000 = 0;
1019 switch (option) {
1020 case _10_Half:
1021 Cap10_100 = PHY_Cap_10_Half;
1022 Cap1000 = PHY_Cap_Null;
1023 break;
1024 case _10_Full:
1025 Cap10_100 = PHY_Cap_10_Full;
1026 Cap1000 = PHY_Cap_Null;
1027 break;
1028 case _100_Half:
1029 Cap10_100 = PHY_Cap_100_Half;
1030 Cap1000 = PHY_Cap_Null;
1031 break;
1032 case _100_Full:
1033 Cap10_100 = PHY_Cap_100_Full;
1034 Cap1000 = PHY_Cap_Null;
1035 break;
1036 case _1000_Full:
1037 Cap10_100 = PHY_Cap_Null;
1038 Cap1000 = PHY_Cap_1000_Full;
1039 break;
1040 default:
1041 break;
1042 }
1043 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
1044 mdio_write(PHY_1000_CTRL_REG, Cap1000);
1045 } else {
1046 #ifdef DEBUG_RTL8169
1047 printf("%s: Auto-negotiation Enabled.\n",
1048 name);
1049 #endif
1050 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
1051 mdio_write(PHY_AUTO_NEGO_REG,
1052 PHY_Cap_10_Half | PHY_Cap_10_Full |
1053 PHY_Cap_100_Half | PHY_Cap_100_Full |
1054 (val & 0x1F));
1055
1056 /* enable 1000 Full Mode */
1057 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
1058
1059 }
1060
1061 /* Enable auto-negotiation and restart auto-nigotiation */
1062 mdio_write(PHY_CTRL_REG,
1063 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
1064 udelay(100);
1065
1066 /* wait for auto-negotiation process */
1067 for (i = 10000; i > 0; i--) {
1068 /* check if auto-negotiation complete */
1069 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
1070 udelay(100);
1071 option = RTL_R8(PHYstatus);
1072 if (option & _1000bpsF) {
1073 #ifdef DEBUG_RTL8169
1074 printf("%s: 1000Mbps Full-duplex operation.\n",
1075 name);
1076 #endif
1077 } else {
1078 #ifdef DEBUG_RTL8169
1079 printf("%s: %sMbps %s-duplex operation.\n",
1080 name,
1081 (option & _100bps) ? "100" :
1082 "10",
1083 (option & FullDup) ? "Full" :
1084 "Half");
1085 #endif
1086 }
1087 break;
1088 } else {
1089 udelay(100);
1090 }
1091 } /* end for-loop to wait for auto-negotiation process */
1092
1093 } else {
1094 udelay(100);
1095 #ifdef DEBUG_RTL8169
1096 printf
1097 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
1098 name,
1099 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
1100 #endif
1101 }
1102
1103
1104 tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC);
1105 if (!tpc->RxDescArray)
1106 return -ENOMEM;
1107
1108 tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC);
1109 if (!tpc->TxDescArray)
1110 return -ENOMEM;
1111
1112 return 0;
1113 }
1114
1115 #ifndef CONFIG_DM_ETH
rtl8169_initialize(bd_t * bis)1116 int rtl8169_initialize(bd_t *bis)
1117 {
1118 pci_dev_t devno;
1119 int card_number = 0;
1120 struct eth_device *dev;
1121 u32 iobase;
1122 int idx=0;
1123
1124 while(1){
1125 unsigned int region;
1126 u16 device;
1127 int err;
1128
1129 /* Find RTL8169 */
1130 if ((devno = pci_find_devices(supported, idx++)) < 0)
1131 break;
1132
1133 pci_read_config_word(devno, PCI_DEVICE_ID, &device);
1134 switch (device) {
1135 case 0x8168:
1136 region = 2;
1137 break;
1138
1139 default:
1140 region = 1;
1141 break;
1142 }
1143
1144 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase);
1145 iobase &= ~0xf;
1146
1147 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
1148
1149 dev = (struct eth_device *)malloc(sizeof *dev);
1150 if (!dev) {
1151 printf("Can not allocate memory of rtl8169\n");
1152 break;
1153 }
1154
1155 memset(dev, 0, sizeof(*dev));
1156 sprintf (dev->name, "RTL8169#%d", card_number);
1157
1158 dev->priv = (void *)(unsigned long)devno;
1159 dev->iobase = (int)pci_mem_to_phys(devno, iobase);
1160
1161 dev->init = rtl_reset;
1162 dev->halt = rtl_halt;
1163 dev->send = rtl_send;
1164 dev->recv = rtl_recv;
1165
1166 err = rtl_init(dev->iobase, dev->name, dev->enetaddr);
1167 if (err < 0) {
1168 printf(pr_fmt("failed to initialize card: %d\n"), err);
1169 free(dev);
1170 continue;
1171 }
1172
1173 eth_register (dev);
1174
1175 card_number++;
1176 }
1177 return card_number;
1178 }
1179 #endif
1180
1181 #ifdef CONFIG_DM_ETH
rtl8169_eth_probe(struct udevice * dev)1182 static int rtl8169_eth_probe(struct udevice *dev)
1183 {
1184 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
1185 struct rtl8169_private *priv = dev_get_priv(dev);
1186 struct eth_pdata *plat = dev_get_platdata(dev);
1187 u32 iobase;
1188 int region;
1189 int ret;
1190
1191 debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
1192 switch (pplat->device) {
1193 case 0x8168:
1194 region = 2;
1195 break;
1196 default:
1197 region = 1;
1198 break;
1199 }
1200 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0 + region * 4, &iobase);
1201 iobase &= ~0xf;
1202 priv->iobase = (int)dm_pci_mem_to_phys(dev, iobase);
1203
1204 ret = rtl_init(priv->iobase, dev->name, plat->enetaddr);
1205 if (ret < 0) {
1206 printf(pr_fmt("failed to initialize card: %d\n"), ret);
1207 return ret;
1208 }
1209
1210 return 0;
1211 }
1212
1213 static const struct eth_ops rtl8169_eth_ops = {
1214 .start = rtl8169_eth_start,
1215 .send = rtl8169_eth_send,
1216 .recv = rtl8169_eth_recv,
1217 .stop = rtl8169_eth_stop,
1218 .write_hwaddr = rtl8169_write_hwaddr,
1219 };
1220
1221 static const struct udevice_id rtl8169_eth_ids[] = {
1222 { .compatible = "realtek,rtl8169" },
1223 { }
1224 };
1225
1226 U_BOOT_DRIVER(eth_rtl8169) = {
1227 .name = "eth_rtl8169",
1228 .id = UCLASS_ETH,
1229 .of_match = rtl8169_eth_ids,
1230 .probe = rtl8169_eth_probe,
1231 .ops = &rtl8169_eth_ops,
1232 .priv_auto_alloc_size = sizeof(struct rtl8169_private),
1233 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1234 };
1235
1236 U_BOOT_PCI_DEVICE(eth_rtl8169, supported);
1237 #endif
1238