1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 samtec automotive software & electronics gmbh
4 * Copyright (C) 2017-2019 softing automotive electronics gmbH
5 *
6 * Author: Christoph Fritz <chf.fritz@googlemail.com>
7 */
8
9 #include <init.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/gpio.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/io.h>
19 #include <asm/mach-imx/mxc_i2c.h>
20 #include <env.h>
21 #include <linux/sizes.h>
22 #include <common.h>
23 #include <fsl_esdhc_imx.h>
24 #include <mmc.h>
25 #include <i2c.h>
26 #include <miiphy.h>
27 #include <netdev.h>
28 #include <power/pmic.h>
29 #include <power/pfuze100_pmic.h>
30 #include <usb.h>
31 #include <usb/ehci-ci.h>
32 #include <pwm.h>
33 #include <wait_bit.h>
34
35 DECLARE_GLOBAL_DATA_PTR;
36
37 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
38 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
39 PAD_CTL_SRE_FAST)
40
41 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE | \
42 PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
43 PAD_CTL_SRE_FAST)
44
45 #define ENET_CLK_PAD_CTRL PAD_CTL_DSE_34ohm
46
47 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | \
48 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH | \
49 PAD_CTL_SRE_FAST)
50
51 #define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
52 PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \
53 PAD_CTL_DSE_40ohm)
54
55 #define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
56 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
57
58 #define USDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
59 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
60 PAD_CTL_SRE_FAST)
61
62 #define USDHC_RESET_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
63 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm)
64
65 #define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
66 PAD_CTL_PKE)
67
dram_init(void)68 int dram_init(void)
69 {
70 gd->ram_size = imx_ddr_size();
71
72 return 0;
73 }
74
75 static iomux_v3_cfg_t const pwm_led_pads[] = {
76 MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
77 MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
78 MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
79 };
80
board_net_init(void)81 static int board_net_init(void)
82 {
83 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
84 unsigned char eth1addr[6];
85 int ret;
86
87 /* just to get second mac address */
88 imx_get_mac_from_fuse(1, eth1addr);
89 if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
90 eth_env_set_enetaddr("eth1addr", eth1addr);
91
92 /*
93 * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
94 * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
95 * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
96 */
97 clrsetbits_le32(&iomuxc_regs->gpr[1],
98 IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
99 IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
100 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
101 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
102
103 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
104 if (ret)
105 goto eth_fail;
106
107 ret = enable_fec_anatop_clock(1, ENET_50MHZ);
108 if (ret)
109 goto eth_fail;
110
111 return ret;
112
113 eth_fail:
114 printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
115 return ret;
116 }
117
118 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
119 /* I2C1 for PMIC */
120 static struct i2c_pads_info i2c_pad_info1 = {
121 .scl = {
122 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
123 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
124 .gp = IMX_GPIO_NR(1, 0),
125 },
126 .sda = {
127 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
128 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
129 .gp = IMX_GPIO_NR(1, 1),
130 },
131 };
132
pfuze_init(unsigned char i2cbus)133 static struct pmic *pfuze_init(unsigned char i2cbus)
134 {
135 struct pmic *p;
136 int ret;
137 u32 reg;
138
139 ret = power_pfuze100_init(i2cbus);
140 if (ret)
141 return NULL;
142
143 p = pmic_get("PFUZE100");
144 ret = pmic_probe(p);
145 if (ret)
146 return NULL;
147
148 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
149 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
150
151 /* Set SW1AB stanby volage to 0.975V */
152 pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
153 reg &= ~SW1x_STBY_MASK;
154 reg |= SW1x_0_975V;
155 pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
156
157 /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
158 pmic_reg_read(p, PFUZE100_SW1ABCONF, ®);
159 reg &= ~SW1xCONF_DVSSPEED_MASK;
160 reg |= SW1xCONF_DVSSPEED_4US;
161 pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
162
163 /* Set SW1C standby voltage to 0.975V */
164 pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
165 reg &= ~SW1x_STBY_MASK;
166 reg |= SW1x_0_975V;
167 pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
168
169 /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
170 pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
171 reg &= ~SW1xCONF_DVSSPEED_MASK;
172 reg |= SW1xCONF_DVSSPEED_4US;
173 pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
174
175 return p;
176 }
177
pfuze_mode_init(struct pmic * p,u32 mode)178 static int pfuze_mode_init(struct pmic *p, u32 mode)
179 {
180 unsigned char offset, i, switch_num;
181 u32 id;
182 int ret;
183
184 pmic_reg_read(p, PFUZE100_DEVICEID, &id);
185 id = id & 0xf;
186
187 if (id == 0) {
188 switch_num = 6;
189 offset = PFUZE100_SW1CMODE;
190 } else if (id == 1) {
191 switch_num = 4;
192 offset = PFUZE100_SW2MODE;
193 } else {
194 printf("Not supported, id=%d\n", id);
195 return -EINVAL;
196 }
197
198 ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
199 if (ret < 0) {
200 printf("Set SW1AB mode error!\n");
201 return ret;
202 }
203
204 for (i = 0; i < switch_num - 1; i++) {
205 ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
206 if (ret < 0) {
207 printf("Set switch 0x%x mode error!\n",
208 offset + i * SWITCH_SIZE);
209 return ret;
210 }
211 }
212
213 return ret;
214 }
215
power_init_board(void)216 int power_init_board(void)
217 {
218 struct pmic *p;
219 int ret;
220
221 p = pfuze_init(I2C_PMIC);
222 if (!p)
223 return -ENODEV;
224
225 ret = pfuze_mode_init(p, APS_PFM);
226 if (ret < 0)
227 return ret;
228
229 set_ldo_voltage(LDO_ARM, 1175); /* Set VDDARM to 1.175V */
230 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
231
232 return 0;
233 }
234
235 #ifdef CONFIG_USB_EHCI_MX6
236 static iomux_v3_cfg_t const usb_otg_pads[] = {
237 /* OGT1 */
238 MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
239 MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
240 /* OTG2 */
241 MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
242 };
243
setup_iomux_usb(void)244 static void setup_iomux_usb(void)
245 {
246 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
247 ARRAY_SIZE(usb_otg_pads));
248 }
249
board_usb_phy_mode(int port)250 int board_usb_phy_mode(int port)
251 {
252 if (port == 1)
253 return USB_INIT_HOST;
254 else
255 return usb_phy_mode(port);
256 }
257 #endif
258
259 #ifdef CONFIG_PWM_IMX
set_pwm_leds(void)260 static int set_pwm_leds(void)
261 {
262 int ret;
263
264 imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
265 ARRAY_SIZE(pwm_led_pads));
266 /* enable backlight PWM 2, green LED */
267 ret = pwm_init(1, 0, 0);
268 if (ret)
269 goto error;
270 /* duty cycle 200ns, period: 8000ns */
271 ret = pwm_config(1, 200, 8000);
272 if (ret)
273 goto error;
274 ret = pwm_enable(1);
275 if (ret)
276 goto error;
277
278 /* enable backlight PWM 1, blue LED */
279 ret = pwm_init(0, 0, 0);
280 if (ret)
281 goto error;
282 /* duty cycle 200ns, period: 8000ns */
283 ret = pwm_config(0, 200, 8000);
284 if (ret)
285 goto error;
286 ret = pwm_enable(0);
287 if (ret)
288 goto error;
289
290 /* enable backlight PWM 6, red LED */
291 ret = pwm_init(5, 0, 0);
292 if (ret)
293 goto error;
294 /* duty cycle 200ns, period: 8000ns */
295 ret = pwm_config(5, 200, 8000);
296 if (ret)
297 goto error;
298 ret = pwm_enable(5);
299
300 error:
301 return ret;
302 }
303 #else
set_pwm_leds(void)304 static int set_pwm_leds(void)
305 {
306 return 0;
307 }
308 #endif
309
310 #define ADCx_HC0 0x00
311 #define ADCx_HS 0x08
312 #define ADCx_HS_C0 BIT(0)
313 #define ADCx_R0 0x0c
314 #define ADCx_CFG 0x14
315 #define ADCx_CFG_SWMODE 0x308
316 #define ADCx_GC 0x18
317 #define ADCx_GC_CAL BIT(7)
318
read_adc(u32 * val)319 static int read_adc(u32 *val)
320 {
321 int ret;
322 void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
323
324 /* use software mode */
325 writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
326
327 /* start auto calibration */
328 setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
329 ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
330 if (ret)
331 goto adc_exit;
332
333 /* start conversion */
334 writel(0, b + ADCx_HC0);
335
336 /* wait for conversion */
337 ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
338 if (ret)
339 goto adc_exit;
340
341 /* read result */
342 *val = readl(b + ADCx_R0);
343
344 adc_exit:
345 if (ret)
346 printf("ADC failure (ret=%i)\n", ret);
347 unmap_physmem(b, MAP_NOCACHE);
348 return ret;
349 }
350
351 #define VAL_UPPER 2498
352 #define VAL_LOWER 1550
353
set_pin_state(void)354 static int set_pin_state(void)
355 {
356 u32 val;
357 int ret;
358
359 ret = read_adc(&val);
360 if (ret)
361 return ret;
362
363 if (val >= VAL_UPPER)
364 env_set("pin_state", "connected");
365 else if (val < VAL_UPPER && val > VAL_LOWER)
366 env_set("pin_state", "open");
367 else
368 env_set("pin_state", "button");
369
370 return ret;
371 }
372
board_late_init(void)373 int board_late_init(void)
374 {
375 int ret;
376
377 ret = set_pwm_leds();
378 if (ret)
379 return ret;
380
381 ret = set_pin_state();
382
383 return ret;
384 }
385
board_early_init_f(void)386 int board_early_init_f(void)
387 {
388 setup_iomux_usb();
389
390 return 0;
391 }
392
board_init(void)393 int board_init(void)
394 {
395 /* Address of boot parameters */
396 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
397
398 #ifdef CONFIG_SYS_I2C_MXC
399 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
400 #endif
401
402 return board_net_init();
403 }
404
checkboard(void)405 int checkboard(void)
406 {
407 puts("Board: VIN|ING 2000\n");
408
409 return 0;
410 }
411
412 #define PCIE_PHY_PUP_REQ BIT(7)
413
board_preboot_os(void)414 void board_preboot_os(void)
415 {
416 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
417 struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
418
419 /* Bring the PCI power domain up, so that old vendorkernel works. */
420 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
421 setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
422 setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
423 }
424
425 #ifdef CONFIG_SPL_BUILD
426 #include <linux/libfdt.h>
427 #include <spl.h>
428 #include <asm/arch/mx6-ddr.h>
429
430 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR };
431
432 static iomux_v3_cfg_t const pcie_pads[] = {
433 MX6_PAD_NAND_DATA02__GPIO4_IO_6 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
434 };
435
436 static iomux_v3_cfg_t const uart_pads[] = {
437 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
438 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
439 };
440
441 static iomux_v3_cfg_t const usdhc4_pads[] = {
442 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
443 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
444 MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
445 MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
446 MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
447 MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
448 MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
449 MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
450 MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
451 MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
452 };
453
vining2000_spl_setup_iomux_pcie(void)454 static void vining2000_spl_setup_iomux_pcie(void)
455 {
456 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
457 }
458
vining2000_spl_setup_iomux_uart(void)459 static void vining2000_spl_setup_iomux_uart(void)
460 {
461 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
462 }
463
board_mmc_init(bd_t * bis)464 int board_mmc_init(bd_t *bis)
465 {
466 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
467 u32 val;
468 u32 port;
469
470 val = readl(&src_regs->sbmr1);
471
472 if ((val & 0xc0) != 0x40) {
473 printf("Not boot from USDHC!\n");
474 return -EINVAL;
475 }
476
477 port = (val >> 11) & 0x3;
478 printf("port %d\n", port);
479 switch (port) {
480 case 3:
481 imx_iomux_v3_setup_multiple_pads(
482 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
483 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
484 usdhc_cfg.esdhc_base = USDHC4_BASE_ADDR;
485 break;
486 }
487
488 gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
489 return fsl_esdhc_initialize(bis, &usdhc_cfg);
490 }
491
board_mmc_getcd(struct mmc * mmc)492 int board_mmc_getcd(struct mmc *mmc)
493 {
494 return 1;
495 }
496
497 const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
498 .dram_dqm0 = 0x00000028,
499 .dram_dqm1 = 0x00000028,
500 .dram_dqm2 = 0x00000028,
501 .dram_dqm3 = 0x00000028,
502 .dram_ras = 0x00000028,
503 .dram_cas = 0x00000028,
504 .dram_odt0 = 0x00000028,
505 .dram_odt1 = 0x00000028,
506 .dram_sdba2 = 0x00000000,
507 .dram_sdcke0 = 0x00003000,
508 .dram_sdcke1 = 0x00003000,
509 .dram_sdclk_0 = 0x00000030,
510 .dram_sdqs0 = 0x00000028,
511 .dram_sdqs1 = 0x00000028,
512 .dram_sdqs2 = 0x00000028,
513 .dram_sdqs3 = 0x00000028,
514 .dram_reset = 0x00000028,
515 };
516
517 const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
518 .grp_addds = 0x00000028,
519 .grp_b0ds = 0x00000028,
520 .grp_b1ds = 0x00000028,
521 .grp_b2ds = 0x00000028,
522 .grp_b3ds = 0x00000028,
523 .grp_ctlds = 0x00000028,
524 .grp_ddr_type = 0x000c0000,
525 .grp_ddrmode = 0x00020000,
526 .grp_ddrmode_ctl = 0x00020000,
527 .grp_ddrpke = 0x00000000,
528 };
529
530 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
531 .p0_mpwldectrl0 = 0x0022001C,
532 .p0_mpwldectrl1 = 0x001F001A,
533 .p0_mpdgctrl0 = 0x01380134,
534 .p0_mpdgctrl1 = 0x0124011C,
535 .p0_mprddlctl = 0x42404444,
536 .p0_mpwrdlctl = 0x36383C38,
537 };
538
539 static struct mx6_ddr3_cfg mem_ddr = {
540 .mem_speed = 1600,
541 .density = 4,
542 .width = 32,
543 .banks = 8,
544 .rowaddr = 15,
545 .coladdr = 10,
546 .pagesz = 2,
547 .trcd = 1391,
548 .trcmin = 4875,
549 .trasmin = 3500,
550 };
551
ccgr_init(void)552 static void ccgr_init(void)
553 {
554 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
555
556 writel(0xF000000F, &ccm->CCGR0); /* AIPS_TZ{1,2,3} */
557 writel(0x303C0000, &ccm->CCGR1); /* GPT, OCRAM */
558 writel(0x00FFFCC0, &ccm->CCGR2); /* IPMUX, I2C1, I2C3 */
559 writel(0x3F300030, &ccm->CCGR3); /* OCRAM, MMDC, ENET */
560 writel(0x0000C003, &ccm->CCGR4); /* PCI, PL301 */
561 writel(0x0F0330C3, &ccm->CCGR5); /* UART, ROM */
562 writel(0x00000F00, &ccm->CCGR6); /* SDHI4, EIM */
563 }
564
vining2000_spl_dram_init(void)565 static void vining2000_spl_dram_init(void)
566 {
567 struct mx6_ddr_sysinfo sysinfo = {
568 .dsize = mem_ddr.width / 32,
569 .cs_density = 24,
570 .ncs = 1,
571 .cs1_mirror = 0,
572 .rtt_wr = 1, /* RTT_wr = RZQ/4 */
573 .rtt_nom = 1, /* RTT_Nom = RZQ/4 */
574 .walat = 1, /* Write additional latency */
575 .ralat = 5, /* Read additional latency */
576 .mif3_mode = 3, /* Command prediction working mode */
577 .bi_on = 1, /* Bank interleaving enabled */
578 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
579 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
580 .ddr_type = DDR_TYPE_DDR3,
581 .refsel = 1, /* Refresh cycles at 32KHz */
582 .refr = 7, /* 8 refresh commands per refresh cycle */
583 };
584
585 mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
586 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
587
588 /* Perform DDR DRAM calibration */
589 udelay(100);
590 mmdc_do_write_level_calibration(&sysinfo);
591 mmdc_do_dqs_calibration(&sysinfo);
592 }
593
board_init_f(ulong dummy)594 void board_init_f(ulong dummy)
595 {
596 /* setup AIPS and disable watchdog */
597 arch_cpu_init();
598
599 ccgr_init();
600
601 /* iomux setup */
602 vining2000_spl_setup_iomux_pcie();
603 vining2000_spl_setup_iomux_uart();
604
605 /* setup GP timer */
606 timer_init();
607
608 /* reset the PCIe device */
609 gpio_set_value(IMX_GPIO_NR(4, 6), 1);
610 udelay(50);
611 gpio_set_value(IMX_GPIO_NR(4, 6), 0);
612
613 /* UART clocks enabled and gd valid - init serial console */
614 preloader_console_init();
615
616 /* DDR initialization */
617 vining2000_spl_dram_init();
618
619 /* Clear the BSS. */
620 memset(__bss_start, 0, __bss_end - __bss_start);
621
622 /* load/boot image from boot device */
623 board_init_r(NULL, 0);
624 }
625 #endif
626