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Searched refs:V2D (Results 1 – 13 of 13) sorted by relevance

/external/vixl/test/aarch64/
Dtest-assembler-neon-aarch64.cc438 __ Ld1(v30.V2D(), v31.V2D(), v0.V2D(), v1.V2D(), MemOperand(x17)); in TEST()
486 __ Ld1(v30.V2D(), in TEST()
487 v31.V2D(), in TEST()
488 v0.V2D(), in TEST()
489 v1.V2D(), in TEST()
680 __ Ld2(v31.V2D(), v0.V2D(), MemOperand(x17)); in TEST()
720 __ Ld2(v31.V2D(), v0.V2D(), MemOperand(x21, 32, PostIndex)); in TEST()
947 __ Ld2r(v12.V2D(), v13.V2D(), MemOperand(x17)); in TEST()
989 __ Ld2r(v12.V2D(), v13.V2D(), MemOperand(x17, 16, PostIndex)); in TEST()
1123 __ Ld3(v31.V2D(), v0.V2D(), v1.V2D(), MemOperand(x17)); in TEST()
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Dtest-trace-aarch64.cc615 __ abs(v0.V2D(), v31.V2D()); in GenerateTestSequenceNEON()
623 __ add(v10.V2D(), v31.V2D(), v14.V2D()); in GenerateTestSequenceNEON()
629 __ addhn(v10.V2S(), v14.V2D(), v15.V2D()); in GenerateTestSequenceNEON()
633 __ addhn2(v0.V4S(), v2.V2D(), v17.V2D()); in GenerateTestSequenceNEON()
635 __ addp(d14, v19.V2D()); in GenerateTestSequenceNEON()
637 __ addp(v8.V2D(), v5.V2D(), v17.V2D()); in GenerateTestSequenceNEON()
678 __ cmeq(v12.V2D(), v16.V2D(), v10.V2D()); in GenerateTestSequenceNEON()
679 __ cmeq(v8.V2D(), v22.V2D(), 0); in GenerateTestSequenceNEON()
694 __ cmge(v28.V2D(), v20.V2D(), v26.V2D()); in GenerateTestSequenceNEON()
695 __ cmge(v6.V2D(), v23.V2D(), 0); in GenerateTestSequenceNEON()
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Dtest-cpu-features-aarch64.cc762 TEST_NEON(abs_6, abs(v0.V2D(), v1.V2D()))
766 TEST_NEON(addhn_2, addhn(v0.V2S(), v1.V2D(), v2.V2D()))
769 TEST_NEON(addhn2_2, addhn2(v0.V4S(), v1.V2D(), v2.V2D()))
770 TEST_NEON(addp_0, addp(d0, v1.V2D()))
777 TEST_NEON(addp_7, addp(v0.V2D(), v1.V2D(), v2.V2D()))
789 TEST_NEON(add_6, add(v0.V2D(), v1.V2D(), v2.V2D()))
823 TEST_NEON(cmeq_6, cmeq(v0.V2D(), v1.V2D(), v2.V2D()))
831 TEST_NEON(cmeq_14, cmeq(v0.V2D(), v1.V2D(), 0))
839 TEST_NEON(cmge_6, cmge(v0.V2D(), v1.V2D(), v2.V2D()))
847 TEST_NEON(cmge_14, cmge(v0.V2D(), v1.V2D(), 0))
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Dtest-disasm-neon-aarch64.cc311 V(V2D(), "2d")
319 V(V2D(), "2d", V4S(), "4s")
324 V(V2D(), "2d", V2S(), "2s")
329 V(V2D(), "2d", V4S(), "4s")
415 COMPARE_MACRO(Ld1(v23.V2D(), in TEST()
416 v24.V2D(), in TEST()
417 v25.V2D(), in TEST()
418 v26.V2D(), in TEST()
442 COMPARE_MACRO(Ld4(v23.V2D(), in TEST()
443 v24.V2D(), in TEST()
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Dtest-api-aarch64.cc256 VIXL_CHECK(q0.V2D().IsValidVRegister()); in TEST()
257 VIXL_CHECK(!q0.V2D().IsValidFPRegister()); in TEST()
/external/v8/src/wasm/baseline/arm64/
Dliftoff-assembler-arm64.h1503 Sxtl(dst.fp().V2D(), dst.fp().V2S()); in LoadTransform()
1506 Uxtl(dst.fp().V2D(), dst.fp().V2S()); in LoadTransform()
1537 ld1r(dst.fp().V2D(), src_op); in LoadTransform()
1550 Dup(dst.fp().V2D(), src.fp().D(), 0); in emit_f64x2_splat()
1556 Mov(dst.fp().D(), lhs.fp().V2D(), imm_lane_idx); in emit_f64x2_extract_lane()
1564 Mov(dst.fp().V2D(), src1.fp().V2D()); in emit_f64x2_replace_lane()
1566 Mov(dst.fp().V2D(), imm_lane_idx, src2.fp().V2D(), 0); in emit_f64x2_replace_lane()
1571 Fabs(dst.fp().V2D(), src.fp().V2D()); in emit_f64x2_abs()
1576 Fneg(dst.fp().V2D(), src.fp().V2D()); in emit_f64x2_neg()
1581 Fsqrt(dst.fp().V2D(), src.fp().V2D()); in emit_f64x2_sqrt()
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/external/v8/src/compiler/backend/arm64/
Dcode-generator-arm64.cc1978 __ Dup(i.OutputSimd128Register().V2D(), i.InputSimd128Register(0).D(), 0); in AssembleArchInstruction()
1982 __ Mov(i.OutputSimd128Register().D(), i.InputSimd128Register(0).V2D(), in AssembleArchInstruction()
1987 VRegister dst = i.OutputSimd128Register().V2D(), in AssembleArchInstruction()
1988 src1 = i.InputSimd128Register(0).V2D(); in AssembleArchInstruction()
1992 __ Mov(dst, i.InputInt8(1), i.InputSimd128Register(2).V2D(), 0); in AssembleArchInstruction()
2006 VRegister dst = i.OutputSimd128Register().V2D(); in AssembleArchInstruction()
2007 __ Fcmeq(dst, i.InputSimd128Register(0).V2D(), in AssembleArchInstruction()
2008 i.InputSimd128Register(1).V2D()); in AssembleArchInstruction()
2013 __ Fcmgt(i.OutputSimd128Register().V2D(), i.InputSimd128Register(1).V2D(), in AssembleArchInstruction()
2014 i.InputSimd128Register(0).V2D()); in AssembleArchInstruction()
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/external/vixl/benchmarks/aarch64/
Dbench-utils.cc380 __ Umull(PickV().V2D(), PickV().V2S(), PickV().V2S()); in GenerateNEONSequence()
/external/vixl/src/aarch64/
Dmacro-assembler-aarch64.cc999 movi(vd.Is64Bits() ? vd.V1D() : vd.V2D(), ((imm << 32) | imm)); in Movi32bitHelper()
1091 dup(vd.V2D(), temp); in Movi64bitHelper()
1126 Movi(vd.V2D(), lo); in Movi()
1129 Ins(vd.V2D(), 1, temp); in Movi()
Doperands-aarch64.h374 VRegister V2D() const { return VRegister(code_, kQRegSize, 2); } in V2D() function
/external/v8/src/codegen/arm64/
Dmacro-assembler-arm64.cc388 movi(vd.Is64Bits() ? vd.V1D() : vd.V2D(), ((imm << 32) | imm)); in Movi32bitHelper()
479 dup(vd.V2D(), temp); in Movi64bitHelper()
508 Movi(vd.V2D(), lo); in Movi()
513 Ins(vd.V2D(), 1, temp); in Movi()
Dregister-arm64.h342 VRegister V2D() const { in V2D() function
/external/cldr/tools/java/org/unicode/cldr/util/data/external/
D2013-1_UNLOCODE_CodeListPart1.csv43210 "+","FR","V2D","Veyrier-du-Lac","Veyrier-du-Lac","74","--3-----","RL","1301",,"4552N 00610E",