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Searched refs:VIRGL_CMD_BLIT_DST_W (Results 1 – 4 of 4) sorted by relevance

/external/crosvm/gpu_renderer/src/generated/
Dvirgl_protocol.rs153 pub const VIRGL_CMD_BLIT_DST_W: u32 = 10; constant
/external/virglrenderer/src/
Dvirgl_protocol.h423 #define VIRGL_CMD_BLIT_DST_W 10 macro
Dvrend_decode.c964 info.dst.box.width = get_buf_entry(ctx, VIRGL_CMD_BLIT_DST_W); in vrend_decode_blit()
/external/mesa3d/src/virtio/virtio-gpu/
Dvirgl_protocol.h436 #define VIRGL_CMD_BLIT_DST_W 10 macro